Texas Instruments SN65LVDS31-32, SN65LVDS31-32A, SN65LVDS31D, SN65LVDS31DR, SN65LVDS31NS Datasheet

SN55LVDS31, SN65LVDS31, SN65LVDS3487, SN65LVDS9638

HIGH-SPEED DIFFERENTIAL LINE DRIVERS

SLLS261F – JULY 1997 – REVISED MARCH 2000

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Meets or Exceeds the Requirements of
ANSI TIA/EIA-644 Standard

D

Low-Voltage Differential Signaling With
Typical Output Voltage of 350 mV and a
100-Ω Load

D

Typical Output Voltage Rise and Fall Times
of 500 ps (400 Mbps)

D

Typical Propagation Delay Times of 1.7 ns

D

Operates From a Single 3.3-V Supply

D

Power Dissipation 25 mW Typical per Driver
at 200 MHz

D

Driver at High Impedance When Disabled or
With VCC = 0

D

Bus-T erminal ESD Protection Exceeds 8 kV

D

Low-Voltage TTL (LVTTL) Logic Input
Levels

D

Pin-Compatible With the AM26LS31,
MC3487, and µA9638

description

The SN55LVDS31, SN65LVDS31,
SN65LVDS3487, and SN65LVDS9638 are
differential line drivers that implement the
electrical characteristics of low-voltage differential
signaling (L VDS). This signaling technique lowers
the output voltage levels of 5 V differential
standard levels (such as TIA/EIA-422B) to reduce
the power, increase the switching speeds, and
allow operation with a 3.3-V supply rail. Any of the
four current-mode drivers will deliver a minimum
differential output voltage magnitude of 247 mV
into a 100-Ω load when enabled.

The intended application of these devices and
signaling technique is for point-to-point baseband
data transmission over controlled impedance
media of approximately 100 Ω. The transmission
media may be printed-circuit board traces,
backplanes, or cables. The ultimate rate and
distance of data transfer is dependent upon the
attenuation characteristics of the media and the
noise coupling to the environment.

The SN65LVDS31, SN65LVDS3487, and
SN65LVDS9638 are characterized for operation
from –40°C to 85°C. The SN55LVDS31 is
characterized for operation from –55°C to 125°C.

Copyright  2000, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

9

1A
1Y

1Z

G

2Z
2Y
2A

GND

V

CC

4A
4Y
4Z
G
3Z
3Y
3A

SN55LVDS31 ... J OR W

SN65LVDS31D

(Marked as LVDS31 or 65LVDS31)

(TOP VIEW)

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

9

1A
1Y

1Z

1,2EN

2Z
2Y
2A

GND

V

CC

4A
4Y
4Z
3,4EN
3Z
3Y
3A

SN65LVDS3487D

(Marked as LVDS3487 or 65LVDS3487)

(TOP VIEW)

1
2
3
4

8
7
6
5

V

CC

1A
2A

GND

1Y
1Z
2Y
2Z

SN65LVDS9638D (Marked as DK638 or LVDS38)

SN65LVDS9638DGN (Marked as L38)

(TOP VIEW)

1920132

17

18

16
15
14

1312119 10

5

4

6
7
8

4Y
4Z
NC
G
3Z

1Z

G

NC

2Z

2Y

1Y1ANCV4A

GND

NC

3A

3Y

2A

SN55LVDS31FK

(TOP VIEW)

CC

SN55LVDS31, SN65LVDS31, SN65LVDS3487, SN65LVDS9638
HIGH-SPEED DIFFERENTIAL LINE DRIVERS

SLLS261F – JULY 1997 – REVISED MARCH 2000

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AVAILABLE OPTIONS

PACKAGE

T

A

SMALL OUTLINE

(D)

MSOP
(DGN)

CHIP CARRIER

(FK)

CERAMIC DIP

(J)

FLAT PACK

(W)

SN65LVDS31D — — — —

–40°C to 85°C

SN65LVDS3487D — — — —
SN65LVDS9638D SN65LVDS9638DGN — — —

–55°C to 125°C — — SN55LVDS31FK SN55LVDS31J SN55LVDS31W

logic symbol

†

SN55LVDS31, SN65LVDS31

4Z

4Y

3Z

3Y

2Z

2Y

1Z

1Y

4A

3A

2A

1A

G

G

13

14

11

10

5

6

3

2

15

9

7

1

12

4

≥ 1

EN

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.

’LVDS31 logic diagram (positive logic)

4Z

4Y

3Z

3Y

2Z

2Y

1Z

1Y

13

14

11

10

5

6

3

2

4A

3A

2A

1A

G

G

15

9

7

1

12

4

SN55LVDS31, SN65LVDS31, SN65LVDS3487, SN65LVDS9638

HIGH-SPEED DIFFERENTIAL LINE DRIVERS

SLLS261F – JULY 1997 – REVISED MARCH 2000

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic symbol

†

EN

EN

4Z

4Y

3Z

3Y

2Z

2Y

1Z

1Y

15

9

12

7

1

4

4A

3A

3,4EN

2A

1A

1,2EN

13

14

11

10

5

6

3

2

SN65LVDS3487

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.

’LVDS3487 logic diagram (positive logic)

4Z

4Y

3Z

3Y

2Z

2Y

1Z

1Y

13

14

11

10

5

6

3

2

4A

3A

2A

1A

15

9

1

4

7

12

3,4EN

1,2EN

logic symbol

†

2Z

2Y

1Z

1Y

3

2

2A

1A

5

6

7

8

SN65LVDS9638

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.

’LVDS9638 logic diagram (positive logic)

2Z

2Y

1Z

1Y

5

6

7

8

2A

1A

2

3

SN55LVDS31, SN65LVDS31, SN65LVDS3487, SN65LVDS9638
HIGH-SPEED DIFFERENTIAL LINE DRIVERS

SLLS261F – JULY 1997 – REVISED MARCH 2000

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Function Tables

SN55LVDS31, SN65LVDS31

INPUT

ENABLES OUTPUTS

A

G

G

Y Z

H H X H L
L H X L H
H X L H L
L X L L H

X L H Z Z
Open H X L H
Open X L L H

H = high level, L = low level, X = irrelevant,
Z = high impedance (off)

SN65LVDS3487

INPUT

ENABLE OUTPUTS

A

EN Y Z

H H H L
L H L H
X L Z Z

OPEN H L H

H = high level, L = low level, X = irrelevant,
Z = high impedance (off)

SN65LVDS9638

INPUT

OUTPUTS

A

Y Z

H H L
L L H

OPEN L H

H = high level, L = low level

SN55LVDS31, SN65LVDS31, SN65LVDS3487, SN65LVDS9638

HIGH-SPEED DIFFERENTIAL LINE DRIVERS

SLLS261F – JULY 1997 – REVISED MARCH 2000

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

equivalent input and output schematic diagrams

7 V

300 kΩ

50 Ω

V

CC

Input

V

CC

5 Ω

7 V

Y or Z
Output

EQUIVALENT OF EACH A INPUT EQUIVALENT OF G, G, 1,2EN OR

3,4EN INPUTS

TYPICAL OF ALL OUTPUTS

7 V

50 Ω

V

CC

Input

10 kΩ

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, VCC (see Note 1) –0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

I

–0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65_C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltages, except differential I/O bus voltages, are with respect to the network ground terminal.

DISSIPATION RATING T ABLE

PACKAGE

TA ≤ 25°C

POWER RATING

DERATING FACTOR

‡

ABOVE TA = 25°C

TA = 70°C

POWER RATING

TA = 85°C

POWER RATING

TA = 125°C

POWER RATING

D (8) 725 mW 5.8 mW/°C 464 mW 377 mW —

D (16) 950 mW 7.6 mW/°C 608 mW 494 mW —

DGN 2.14 W 17.1 mW/°C 1.37 W 1.11 W —

FK 1375 mW 11.0 mW/°C 880 mW 715 mW 275 mW

J 1375 mW 11.0 mW/°C 880 mW 715 mW 275 mW

W 1000 mW 8.0 mW/°C 640 mW 520 mW 200 mW

‡

This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, V

CC

3 3.3 3.6 V

High-level input voltage, V

IH

2 V

Low-level input voltage, V

IL

0.8 V

p

p

SN65 prefix –40 85

°

Operating free-air temperature, T

A

SN55 prefix –55 125

°C

SN55LVDS31, SN65LVDS31, SN65LVDS3487, SN65LVDS9638
HIGH-SPEED DIFFERENTIAL LINE DRIVERS

SLLS261F – JULY 1997 – REVISED MARCH 2000

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN65LVDSxxxx electrical characteristics over recommended operating conditions (unless
otherwise noted)

PARAMETER TEST CONDITIONS

SN65LVDS31,

’3487, ’ 9638

UNIT

MIN TYP†MAX

V

OD

Differential output voltage magnitude

247 340 454 mV

∆V

OD

Change in differential output voltage magnitude
between logic states

RL = 100 Ω, See Figure 2

–50

50 mV

V

OC(SS)

Steady-state common-mode output voltage See Figure 3 1.125 1.2 1.375 mV

∆V

OC(SS)

Change in steady-state common-mode output voltage
between logic states

See Figure 3

–50 50 V

V

OC(PP)

Peak-to-peak common-mode output voltage

g

50 150 mV

VI = 0.8 V or 2 V,
No load

Enabled,

9 20 mA

pp

SN65LVDS31,
’3487

VI = 0.8 or 2 V,
Enabled

RL = 100 Ω,

25 35 mA

ICCSu ly current

VI = 0 or VCC,

Disabled

0.25 1 mA

No load

4.7 8 mA

SN65LVDS9638

V

I

= 0.8 V or 2

V

RL = 100 Ω

9 13 mA

I

IH

High-level input current VIH = 2 4 20 µA

I

IL

Low-level input current VIL = 0.8 V 0.1 10 µA

p

V

O(Y)

or V

O(Z)

= 0 –4 –24 mA

IOSShort-circuit output current

VOD = 0 ±12 mA

I

OZ

High-impedance output current VO = 0 or 2.4 V ±1 µA

I

O(OFF)

Power-off output current VCC = 0, VO = 2.4 V ±1 µA

C

I

Input capacitance 3 pF

†

All typical values are at TA = 25°C and with VCC = 3.3 V.

SN65LVDSxxxx switching characteristics over recommended operating conditions (unless
otherwise noted)

PARAMETER TEST CONDITIONS

SN65LVDS31,

’3487, ’ 9638

UNIT

MIN TYP†MAX

t

pLH

Propagation delay time, low-to-high-level output 0.5 1.4 2 ns

t

pHL

Propagation delay time, high-to-low-level output 1 1.7 2.5 ns

t

r

Differential output signal rise time (20% to 80%)

R

= 100 Ω, C

= 10 pF,

0.4 0.5 0.6 ns

t

f

Differential output signal fall time (80% to 20%)

L

,

L

,

See Figure 2

0.4 0.5 0.6 ns

t

sk(p)

Pulse skew (|t

PHL

– t

PLH

|) 0.3 0.6 ns

t

sk(o)

Channel-to-channel output skew

‡

0 0.3 ns

t

sk(pp)

Part-to-part skew

§

800 ps

t

pZH

Propagation delay time, high-impedance-to-high-level output 5.4 15 ns

t

pZL

Propagation delay time, high-impedance-to-low-level output

2.5 15 ns

t

pHZ

Propagation delay time, high-level-to-high-impedance output

See Figure 4

8.1 15 ns

t

pLZ

Propagation delay time, low-level-to-high-impedance output 7.3 15 ns

†

All typical values are at TA = 25°C and with VCC = 3.3 V.

‡

t

sk(o)

is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same

direction while driving identical specified loads.

§

t

sk(pp)

is the magnitude of the different in propagation delay times between any specified terminals of two devices when both devices operate

with the same supply voltages, same temperature, and have identical packages and test circuits.