TEXAS INSTRUMENTS SN65LVDS33, SN65LVDT33, SN65LVDS34, SN65LVDT34 Technical data

SN65LVDS33, SN65LVDT33, SN65LVDS34, SN65LVDT34

)

HIGH-SPEED DIFFERENTIAL RECEIVERS

SLLS490A – MARCH 2001 – REVISED MA Y 2001

D

400-Mbps Signaling Rate1 and 200-Mxfr/s
Data Transfer Rate

D

Operates With a Single 3.3-V Supply

D

–4-V to 5-V Common-Mode Input Voltage
Range

D

Differential Input Thresholds <±50 mV With
50 mV of Hysteresis Over Entire
Common-Mode Input Voltage Range

D

Integrated 110-Ω Line Termination
Resistors On LVDT Products

D

TSSOP Packaging (33 Only)

D

Complies With TIA/EIA-644 (LVDS)

D

Active Failsafe Assures a High-Level
Output With No Input

D

Bus-Pin ESD Protection Exceeds
15 kV HBM

D

Input Remains High-Impedance on Power
Down

D

TTL Inputs Are 5-V Tolerant

D

Pin-Compatible With the AM26LS32,
SN65LVDS32B, µA9637, SN65LVDS9637B

description

This family of four L VDS data line receivers offers
the widest common-mode input voltage range in
the industry. These receivers provide an input
voltage range specification compatible with a 5-V
PECL signal as well as an overall increased
ground-noise tolerance. They are in industry
standard footprints with integrated termination as
an option.

D OR PW PACKAGE

(TOP VIEW)

1B

1

16

1A

2

15

1Y

3

14

G

4

13

2Y

5

12

2A

6

11

7

2B

GND

V

CC

1Y
2Y

GND

D PACKAGE

(TOP VIEW)

10

8

1
2
3
4

SN65LVDS33D

SN65LVDT33D
SN65LVDS33PW
SN65LVDT33PW

V

CC

4B
4A
4Y
G
3Y
3A

9

3B

SN65LVDS34D
SN65LVDT34D

1A

8

1B

7

2A

6

2B

SN65LVDT34 ONLY

5

logic diagram (positive logic

G
G

SN65LVDT33 ONLY

1A
1B

2A
2B

3A
3B
4A
4B

1Y

2Y

3Y

4Y

logic diagram (positive logic)

1A
1B

2A
2B

1Y

2Y

Precise control of the differential input voltage
thresholds allows for inclusion of 50 mV of input
voltage hysteresis to improve noise rejection on
slowly changing input signals. The input thresh­olds are still no more than ±50 mV over the full
input common-mode voltage range.

The high-speed switching of L VDS signals usually
necessitates the use of a line impedance
matching resistor at the receiving-end of the cable
or transmission media. The SN65LVDT series of
receivers eliminates this external resistor by

PART NUMBER

SN65LVDS33D
SN65LVDS33PW
SN65LVDT33D
SN65LVDT33PW
SN65LVDS34D
SN65LVDT34D

†

Add the suffix R for taped and reeled carrier .

AVAILABLE OPTIONS

NUMBER

†

OF
RECEIVERS

4
4
4
4
2
2

RESISTOR

No

No
Yes
Yes

No
Yes

SYMBOLIZATIONTERMINATION

LVDS33
LVDS33
LVDT33
LVDT33
LVDS34
LVDT34

integrating it with the receiver. The nonterminated
SN65LVDS series is also available for multidrop
or other termination circuits.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1

The signalling rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second).

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  2001, Texas Instruments Incorporated

1

SN65LVDS33, SN65LVDT33, SN65LVDS34, SN65LVDT34

V

≥ -32 mV

100 mV

V

≤ –32 mV

VID≤ –100 mV

Open

HIGH-SPEED DIFFERENTIAL RECEIVERS

SLLS490A – MARCH 2001 – REVISED MAY 2001

description (continued)

The receivers can withstand ±15 kV human-body model (HBM) and ±600 V machine model (MM) electrostatic
discharges to the receiver input pins with respect to ground without damage. This provides reliability in cabled
and other connections where potentially damaging noise is always a threat.

The receivers also include a (patent pending) failsafe circuit that will provide a high-level output within 600 ns
after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines,
or powered-down transmitters. The failsafe circuit prevents noise from being received as valid data under these
fault conditions. This feature may also be used for Wired-Or bus signaling. See The Active Failsafe Feature of
the SN65LVDS32B application note.

The intended application and signaling technique of these devices is point-to-point baseband data transmission
over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board
traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation
characteristics of the media and the noise coupling to the environment.

The SN65L VDS33, SN65LVDT33, SN65LVDS34 and SN65L VDT34 are characterized for operation from –40°C
to 85°C.

Function Tables

SN65LVDS33 and SN65LVDT33 SN65LVDS34 and SN65LVDT34

DIFFERENTIAL INPUT ENABLES OUTPUT DIFFERENTIAL INPUT OUTPUT

VID = VA – V

ID

–

H = high level, L = low level, X = irrelevant,
Z = high impedance (off), ? = indeterminate

<

B

ID

X L H Z

p

G G Y VID = VA – V

H X H
X L H
H X ?
X L ?
H X L
X L L

H X H
X L H

VID ≥ -32 mV H

–100 mV < VID ≤ –32 mV ?

VID≤ -100 mV L

Open H

H = high level, L = low level,
? = indeterminate

B

Y

2

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SN65LVDS33, SN65LVDT33, SN65LVDS34, SN65LVDT34

equivalent input and output schematic diagrams

Attenuation

Network

V

CC

1 pF

200 kΩ

3 pF

60 kΩ

250 kΩ

A Input

7 V
7 V

HIGH-SPEED DIFFERENTIAL RECEIVERS

SLLS490A – MARCH 2001 – REVISED MAY 2001

V

CC

6.5 kΩ 6.5 kΩ

Network

Attenuation

LVDT Only 110 Ω

Network

Attenuation

7 V

7 V

B Input

Enable

Inputs

(G Only)

7 V

300 kΩ

(G

Only)

100 Ω

300 kΩ

V

CC

V

CC

37 Ω

Y Output

7 V

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3

SN65LVDS33, SN65LVDT33, SN65LVDS34, SN65LVDT34

Magnitude of differential input voltage,  VID

V

HIGH-SPEED DIFFERENTIAL RECEIVERS

SLLS490A – MARCH 2001 – REVISED MAY 2001

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage range, V

(see Note 1) –0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

†

Voltage range: Enables or Y –1 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A or B –5 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

V

– VB (LVDT) 1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A

Electrostatic discharge: A, B, and GND (see Note 2) Class 3, A: 15 kV, B: 600 V. . . . . . . . . . . . . . . . . . . . . . .

Charged-device mode: All pins (see Note 3) ±500 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values, except dif ferential I/O bus voltages, are with respect to network ground terminal.

2. Tested in accordance with JEDEC Standard 22, Test Method A114-A.

3. Tested in accordance with JEDEC Standard 22, Test Method C101.

DISSIPATION RATING TABLE

PACKAGE

D8 725 mW 5.8 mW/°C 377 mW

PW16 774 mW 6.2 mW/°C 402 mW

D16 950 mW 7.6 mW/°C 494 mW

‡

This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with
no air flow.

TA ≤ 25°C

POWER RATING

OPERATING FACTOR

ABOVE TA = 25°C

‡

TA = 85°C

POWER RATING

recommended operating conditions

Supply voltage, V
High-level input voltage, V
Low-level input voltage, V

Voltage at any bus terminal (separately or common-mode), VI or V
Operating free-air temperature, T

CC

IH

IL

p

A

Enables 2 5 V
Enables 0 0.8 V
LVDS 0.1 3
LVDT 0.8

MIN NOM MAX UNIT

3 3.3 3.6 V

IC

–4 5 V

–40 85 °C

4

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SN65LVDS33, SN65LVDT33, SN65LVDS34, SN65LVDT34

SN65LVDx33

SN65LVDS

A

IIInput current (A or B inputs)

SN65LVDT

A

I

SN65LVDS

I

A

SN65LVDT

HIGH-SPEED DIFFERENTIAL RECEIVERS

SLLS490A – MARCH 2001 – REVISED MAY 2001

electrical characteristics over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

V

IT1

V

IT2

V

IT3

V

ID(HYS)

V

OH

V

OL

I

CC

ID

I(OFF)

I

IH

I

IL

I

OZ

C

I

†

All typical values are at 25°C and with a 3.3 V supply.

Positive-going differential input voltage threshold 50
Negative-going differential input voltage

threshold
Differential input failsafe voltage threshold See Table 1 and Figure 5 –32 –100 mV
Differential input voltage hysteresis,

V

– V

IT1

IT2

High-level output voltage IOH = –4 mA 2.4 V
Low-level output voltage IOL = 4 mA 0.4 V

Supply current

SN65LVDx34 No load, Steady-state 8 12

p

Differential input current
(IIA – IIB)

Power-off input current
(A or B inputs)

High-level input current (enables) VIH = 2 V 10 µA
Low-level input current (enables) VIL = 0.8 V 10 µA
High-impedance output current –10 10 µA
Input capacitance, A or B input to GND VI = 0.4 sin (4E6πt) + 0.5 V 5 pF

p

SN65LVDS VID = 100 mV, VIC= –4 V or 5 V ±3 µA
SN65LVDT VID = 200 mV, VIC= –4 V or 5 V 1.55 2.22 mA

VIB = –4 V or 5 V, See Figures 1 and 2

G at VCC, No load, Steady-state 16 23
G at GND 1.1 5

VI = 0 V, Other input open ±20
VI = 2.4 V, Other input open ±20
VI = –4 V, Other input open ±75
VI = 5 V, Other input open ±40
VI = 0 V, Other input open ±40
VI = 2.4 V, Other input open ±40
VI = –4 V, Other input open ±150
VI = 5 V, Other input open ±80

VA or VB = 0 V or 2.4 V, VCC = 0 V ±20
VA or VB = –4 or 5 V, VCC = 0 V ±50
VA or VB =0 V or 2.4 V, VCC = 0 V ±30
VA or VB = –4 V or 5 V, VCC = 0 V ±100

–50

50 mV

mV

mA

µ

µ

µ

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5

SN65LVDS33, SN65LVDT33, SN65LVDS34, SN65LVDT34

See Figure 3

L

,

See Figure 4

HIGH-SPEED DIFFERENTIAL RECEIVERS

SLLS490A – MARCH 2001 – REVISED MAY 2001

switching characteristics over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

t

PLH(1)

t

PHL(1)

t

d1

t

d2

t

sk(p)

t

sk(o)

t

sk(pp)

t

r

t

f

t

PHZ

t

PLZ

t

PZH

t

PZL

†

All typical values are at 25°C and with a 3.3-V supply.

‡

t

sk(o)

§

t

sk(pp)

operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.

Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Delay time, failsafe deactivate time
Delay time, failsafe activate time
Pulse skew (|t
Output skew
Part-to-part skew
Output signal rise time 0.8 ns
Output signal fall time 0.8 ns
Propagation delay time, high-level-to-high-impedance output 5.5 9 ns
Propagation delay time, low-level-to-high-impedance output
Propagation delay time, high-impedance -to-high-level output
Propagation delay time, high-impedance-to-low-level output 7 9 ns

is the magnitude of the time difference between the t

is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both devices

‡

PHL(1)

§

– t

|) 200 ps

PLH(1)

or t

PLH

of all receivers of a single device with all of their inputs driven together.

PHL

C

= 10 pF,

See Figures 3 and 6

See Figure 3

2.5 4 6 ns

2.5 4 6 ns
9 ns

0.3 1.5 µs

150 ps

1 ns

4.4 9 ns

3.8 9 ns

6

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