Texas Instruments SN65LVDS301, SN65LVDS301ZQER Datasheet

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Flatlink 3Gä

Application

Processor

with

RGB

Video

Interface

LVDS302

LVDS301

LCD

Driver

DATACLK

PROGRAMMABLE 27-BIT DISPLAY SERIAL INTERFACE TRANSMITTER

SN65LVDS301

SLLS681C – FEBRUARY 2006 – REVISED AUGUST 2006

FEATURES

• FlatLink™3G serial interface technology

• Compatible with FlatLink3G receivers such as

SN65LVDS302

• Input supports 24-bit RGB video mode

interface

• 24-Bit RGB Data, 3 Control Bits, 1 Parity Bit

and 2 Reserved Bits Transmitted over 1, 2 or 3 Differential Lines

• SubLVDS Differential Voltage Levels

• Effective Data Throughput up to 1755 Mbps

• Three Operating Modes to Conserve Power

– Active-Mode QVGA 17.4 mW (typ) – Active-Mode VGA 28.8 mW (typ)

FPC cabling typically interconnects the SN65LVDS301 with the display. Compared to parallel signaling, the LVDS301 outputs significantly reduce the EMI of the interconnect by over 20 dB. The electromagnetic emission of the device itself is very low and meets the meets SAE J1752/3 'M'-spec. (see Figure 37 )

The SN65LVDS301 supports three power modes (Shutdown, Standby and Active) to conserve power. When transmitting, the PLL locks to the incoming pixel clock PCLK and generates an internal high-speed clock at the line rate of the data lines. The parallel data are latched on the rising or falling edge of PCLK as selected by the external control signal CPOL. The serialized data is presented on the serial outputs D0, D1, D2 with a recreated PCLK generated from the internal high-speed clock, output

– Shutdown Mode ≈ 0.5 µ A (typ) on the CLK output. If PCLK stops, the device enters – Standby Mode ≈ 0.5 µ A (typ)

• Bus Swap for Increased PCB Layout

Flexibility

• 1.8-V Supply Voltage

• ESD Rating > 2 kV (HBM)

• Typical Application: Host-Controller to

Display-Module Interface

• Pixel Clock Range of 4 MHz–65 MHz

a standby mode to conserve power The parallel (CMOS) input bus offers a bus-swap

feature. The SWAP pin configures the input order of the pixel data to be either R[7:0]. G[7:0], B[7:0], VS, HS, DE or B[0:7]. G[0:7], R[0:7], VS, HS, DE. This gives a PCB designer the flexibility to better match the bus to the host controller pinout or to put the transmitter device on the top side or the bottom side of the PCB.

• Failsafe on all CMOS Inputs

• Packaging: 80 Pin 5mm × 5mm µ BGA

• Very low EMI meets SAE J1752/3 'M'-spec

DESCRIPTION

The SN65LVDS301 serializer device converts 27 parallel data inputs to 1, 2, or 3 Sub Low-Voltage Differential Signaling (SubLVDS) serial outputs. It loads a shift register with 24 pixel bits and 3 control bits from the parallel CMOS input interface. In addition to the 27 data bits, the device adds a parity bit and two reserved bits into a 30-bit data word. Each word is latched into the device by the pixel clock (PCLK). The parity bit (odd parity) allows a receiver to detect single bit errors. The serial shift register is uploaded at 30, 15, or 10 times the pixel-clock data rate depending on the number of serial links used. A copy of the pixel clock is output on a separate differential output.

FlatLink is a trademark of Texas Instruments. µ BGA is a registered trademark of Tessera, Inc..

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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[0..26]

PLL

multiplier

TXEN

PCLK

B[0:7]

G[0:7]

R[0:7]

LS1

SubLVDS

D0+

D0−

SubLVDS

D2+

D2−

SubLVDS

CLK+

CLK−

SubLVDS

D1+

D1−

LS0

CPOL

SWAP

Parity

Calc

iPCLK

Bit28=0 Bit27=0

3x10, 2x15, or 1x30−bit parallel to serial conversion

Bit29

Glitch

supression

Control /

standby Monitor

x10, x15, or x30

SN65LVDS301

SLLS681C – FEBRUARY 2006 – REVISED AUGUST 2006

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

DESCRIPTION (CONTINUED)

Two Link Select lines LS0 and LS1 control whether 1, 2 or 3 serial links are used. The TXEN input may be used to put the SN65LVDS301 in a shutdown mode. The SN65LVDS301 enters an active Standby mode if the input clock PCLK stops. This minimizes power consumption without the need for controlling an external pin. The SN65LVDS301 is characterized for operation over ambient air temperatures of –40 ° C to 85 ° C. All CMOS inputs offer failsafe features to protect them from damage during power-up and to avoid current flow into the device inputs during power-up. An input voltage of up to 2.165 V can be applied to all CMOS inputs while V between 0V and 1.65V.

Functional Block Diagram

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PINOUT - TOP VIEW

8764 5321

HS VS

PCLK

B1B4B2

G5G3

G1 R3R6R5

R2 R4

R0G4

SN65LVDS301

TopView

SWAP

SWAP=0

8764 5321

HS VS

PCLK

R6R3R5

G2G4

G6 B4B1B2

B5 B3

B7G3

SN65LVDS301

TopView

SWAP

SWAP=1

1.8V

SN65LVDS301

SLLS681C – FEBRUARY 2006 – REVISED AUGUST 2006

SWAP PIN FUNCTIONALITY

The SWAP pin allows the pcb designer to reverse the RGB bus to minimize potential signal crossovers in the PCB routing. The two drawings beneath show the RGB signal pin assignment based on the SWAP-pin setting.

Figure 1. SWAP PIN = 0 Figure 2. SWAP PIN = 1

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SN65LVDS301

SLLS681C – FEBRUARY 2006 – REVISED AUGUST 2006

Table 1. NUMERIC PIN LIST

PIN SWAP SIGNAL PIN SWAP . . SIGNAL PIN SWAP SIGNAL

A1 — GND 0 B6 0 B1

A7 D1

A8 D2

0 G2 1 R1 1 R6 1 G5 0 B7 0 B2 0 G4 1 R0 1 R5 1 G3 C3 UNPOPULATED F3 — VDD 0 G6 C4 — VDD F4 — GND 1 G1 C5 — GND F5 — GND 0 R0 C6 — VDD F6 — GND 1 B7 C7 — VDD F7 — GND 0 R2 C8 — GND F8 — V 1 B5 C9 — LS0 F9 — D1+ 0 R4 0 B4 G1 — PCLK 1 B3 1 R3 0 B0 0 R6 0 B5 1 R7 1 B1 1 R2 G3 — V

A9 — GND D3 — VDD G4 — GND

B4 E1

0 G0 D4 — GND G5 — GND 1 G7 D5 — GND G6 — GND 0 G1 D6 — GND G7 — GND 1 G6 D7 — GND G8 — GND 0 G3 D8 — LS1 G9 — D1– 1 G4 D9 — D2+ H1 — HS 0 G5 0 B3 H2 — VS 1 G2 1 R4 H3 — GND 0 G7 E2 — GND H4 — GND 1 G0 E3 — VDD H5 — V 0 R1 E4 — GND H6 — GND 1 B6 E5 — GND H7 — V 0 R3 E6 — GND H8 — V 1 B4 E7 — GND H9 — CPOL 0 R5 E8 — GND 1 B2 E9 — D2– J2 — DE 0 R7 J3 — TXEN 1 B0 J4 — D0–

C1 F1

C2 F2

PLLD

J1 — GND

J5 — D0+ J6 — CLK– J7 — CLK+ J8 — SWAP J9 — GND

DDPLLD

LVDS

DDLVDS

PLLA DDPLLA DDLVDS

LVDS

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SN65LVDS301

SLLS681C – FEBRUARY 2006 – REVISED AUGUST 2006

TERMINAL FUNCTIONS

NAME I/O DESCRIPTION

D0+, D0– SubLVDS Data Link (active during normal operation) D1+, D1–

SubLVDS Out

D2+, D2– CLK+, CLK– SubLVDS output Clock; clock polarity is fixed

R0–R7 Red Pixel Data (8); pin assignment depends on SWAP pin setting G0–G7 Green Pixel Data (8); pin assignment depends on SWAP pin setting B0–B7 Blue Pixel Data (8); pin assignment depends on SWAP pin setting HS Horizontal Sync VS Vertical Sync DE Data Enable PCLK Input Pixel Clock; rising or falling clock polarity is selected by control input CPOL LS0, LS1 Link Select (Determines active SubLVDS Data Links and PLL Range) See Table 2

CMOS IN

TXEN

CPOL CMOS In

SWAP CMOS In

GND Supply Ground V

DDLVDS

GND

LVDS

DDPLLA

GND

PLLA

DDPLLD

GND

PLLD

Power Supply

(1)

(1) For a multilayer pcb, it is recommended to keep one common GND layer underneath the device and connect all ground terminals

directly to this plane.

SubLVDS Data Link (active during normal operation when LS0 = high and LS1 = low, or LS0 = low and LS1=high; high impedance if LS0 = LS1 = low)

SubLVDS Data Link (active during normal operation when LS0 = low and LS1 = high, high-impedance when LS1 = low)

Disables the CMOS Drivers and Turns Off the PLL, putting device in shutdown mode

1 – Transmitter enabled 0 – Transmitter disabled (Shutdown)

Note: The TXEN input incorporates glitch-suppression logic to avoid device malfunction on short input spikes. It is necessary to pull TXEN high for longer than 10 µ s to enable the transmitter. It is necessary to pull the TXEN input low for longer than 10 µ s to disable the transmitter. At power up, the transmitter is enabled immediately if TXEN = 1 and disabled if TXEN = 0

Input Clock Polarity Selection

0 – rising edge clocking 1 – falling edge clocking

Bus Swap swaps the bus pins to allow device placement on top or bottom of pcb. See pinout drawing for pin assignments.

0 – data input from B0...R7 1 – data input from R7...B0

Supply Voltage

SubLVDS I/O supply Voltage SubLVDS Ground PLL analog supply Voltage PLL analog GND PLL digital supply Voltage PLL digital GND

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D0+/– CHANNEL

CLK+

R2 R1

G7 G6 G5 G4G3G2 G1 G0

B2 B1

VS HS DE

0 0

CP R7

CLK–

R2 R1

G7 G6 G5 G4 VS0CP

G2 G1 G0

B2 B1

HS DE

CP R7

CLK+

CLK–

D0+/– Channel

D1+/– Channel

SN65LVDS301

SLLS681C – FEBRUARY 2006 – REVISED AUGUST 2006

FUNCTIONAL DESCRIPTION

Serialization Modes

The SN65LVDS301 transmitter has three modes of operation controlled by link-select pins LS0 and LS1.

Table 2 shows the serializer modes of operation.

Table 2. Logic Table: Link Select Operating Modes

LS1 LS0 Mode of Operation Data Links Status

0 0 1ChM 1-channel mode (30-bit serialization rate) D0 active;

0 1 2ChM 2-channel mode (15-bit serialization rate) D0, D1 active;

1 0 3ChM 3-channel mode (10-bit serialization rate) D0, D1, D2 active 1 1 Reserved Reserved

1-Channel Mode

While LS0 and LS1 are held low, the SN65LVDS301 transmits payload data over a single SubLVDS data pair, D0. The PLL locks to PCLK and internally multiplies the clock by a factor of 30. The internal high-speed clock is used to serialize (shift out) the data payload on D0. Two reserved bits and the parity bit are added to the data frame. Figure 3 illustrates the timing and the mapping of the data payload into the 30-bit frame. The internal high-speed clock is divided by a factor of 30 to recreate the pixel clock, and presented on the SubLVDS CLK output. While in this mode, the PLL can lock to a clock that is in the range of 4 MHz through 15 MHz. This mode is intended for smaller video display formats (e.g. QVGA to HVGA) that do not require the full bandwidth capabilities of the SN65LVDS301.

D1, D2 high-impedance

D2 high-impedance

Figure 3. Data and Clock Output in 1-Channel Mode (LS0 and LS1 = low).

2-Channel Mode

While LS0 is held high and LS1 is held low, the SN65LVDS301 transmits payload data over two SubLVDS data pairs, D0 and D1. The PLL locks to PCLK and internally multiplies it by a factor of 15. The internal high-speed clock is used to serialize the data payload on D0, and D1. Two reserved bits and the parity bit are added to the data frame. Figure 4 illustrates the timing and the mapping of the data payload into the 30-bit frame and how the frame becomes split into the two output channels. The internal high-speed clock is divided by 15 to recreate the pixel clock, and presented on SubLVDS CLK. The PLL can lock to a clock that is in the range of 8 MHz through 30 MHz in this mode. Typical applications for using the 2-channel mode are HVGA and VGA displays.

Figure 4. Data and Clock Output in 2-Channel Mode (LS0 = high; LS1 = low).

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D0+/-CHANNEL

CLK+

B7 B6

R7 R6 R5 R4 R3 R2 R1 R0

G7 G6 G5 G4 G3 G2 G1 G0

B5 B4 B3 B2 B1 B0

CLK-

B7 B6

R7 R6

G7 G6D1+/-CHANNEL

D2+/-CHANNEL

SN65LVDS301

SLLS681C – FEBRUARY 2006 – REVISED AUGUST 2006

3-Channel Mode

While LS0 is held low and LS1 is held high, the SN65LVDS301 transmits payload data over three SubLVDS data pairs D0, D1, and D2. The PLL locks to PCLK, and internally multiplies it by 10. The internal high-speed clock is used to serialize the data payload on D0, D1, and D2. Two reserved bits and the parity bit are added to the data frame. Figure 5 illustrates the timing and the mapping of the data payload into the 30-bit frame and how the frame becomes split over the three output channels. The internal high speed clock is divided back down by a factor of 10 to recreate the pixel clock and presented on SubLVDS CLK output. While in this mode, the PLL can lock to a clock in the range of 20 MHz through 65 MHz. The 3-channel mode supports applications with very large display resolutions such as VGA or XGA.

Figure 5. Data and Clock Output in 3-Channel Mode (LS0 = low; LS1 = high).

Powerdown Modes

The SN65LVDS301 Transmitter has two powerdown modes to facilitate efficient power management.

Shutdown Mode

The SN65LVDS301 enters Shutdown mode when the TXEN pin is asserted low. This turns off all transmitter circuitry, including the CMOS input, PLL, serializer, and SubLVDS transmitter output stage. All outputs are high-impedance. Current consumption in Shutdown mode is nearly zero.

Standby Mode

The SN65LVDS301 enters the Standby mode if TXEN is high and the PCLK input signal frequency is less than 500kHz. All circuitry except the PCLK input monitor is shut down, and all outputs enter high-impedance mode. The current consumption in Standby mode is very low. When the PCLK input signal is completely stopped, the IDDcurrent consumption is less than 10 µ A. The PCLK input must not be left floating.

NOTE:

A floating (left open) CMOS input allows leakage currents to flow from V To prevent large leakage current, a CMOS gate must be kept at a valid logic level, either V

or VIL. This can be achieved by applying an external voltage of V

all SN65LVDS301 inputs.

to GND.

or V

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Standby

Mode

Transmit

Mode

Acquire

Mode

TXENHigh>10 sm

PowerUp TXEN=0

PowerUp TXEN=1

CLK Active

PLL AchievedLock

Shutdown

Mode

TXENLow

>10 sm

TXENLow

>10 sm

TXENLow

>10 sm

PCLK

StopsorLost

PCLK

StopsorLost

PCLK Active

PowerUp TXEN=1

CLKInactive

SN65LVDS301

SLLS681C – FEBRUARY 2006 – REVISED AUGUST 2006

Active Modes

When TXEN is high and the PCLK input clock signal is faster than 3 MHz, the SN65LVDS301 enters Active mode. Current consumption in Active mode depends on operating frequency and the number of data transitions in the data payload.

Acquire Mode (PLL approaches lock)

The PLL is enabled and attempts to lock to the input Clock. All outputs remain in high-impedance mode. When the PLL monitor detects stable PLL operation, the device switches from Acquire to Transmit mode. For proper device operation, the pixel clock frequency must fall within the valid f operating conditions. If the pixel clock frequency is larger than 3 MHz but smaller than f SN65LVDS301 PLL is enabled. Under such conditions, it is possible for the PLL to lock temporarily to the pixel clock, causing the PLL monitor to release the device into transmit mode. If this happens, the PLL may or may not be properly locked to the pixel clock input, potentially causing data errors, frequency oscillation, and PLL deadlock (loss of VCO oscillation).

Transmit Mode

After the PLL achieves lock, the device enters the normal transmit mode. The CLK pin outputs a copy of PCLK. Based on the selected mode of operation, the D0, D1, and D2 outputs carry the serialized data. In 1-channel mode, outputs D1 and D2 remain high-impedance. In the 2-channel mode, output D2 remains high-impedance.

Parity Bit Generation

The SN65LVDS301 transmitter calculates the parity of the transmit data word and sets the parity bit accordingly. The parity bit covers the 27 bit data payload consisting of 24 bits of pixel data plus VS, HS and DE. The two reserved bits are not included in the parity generation. ODD Parity bit signaling is used. The transmitter sets the Parity bit if the sum of the 27 data bits result in an even number of ones. The Parity bit is cleared otherwise. This allows the receiver to verify Parity and detect single bit errors.

PCLK

range specified under recommended

(min), the

PCLK

Status Detect and Operating Modes Flow diagram

The SN65LVDS301 switches between the power saving and active modes in the following way:

Figure 6. Status Detect and Operating Modes Flow Diagram

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SN65LVDS301

SLLS681C – FEBRUARY 2006 – REVISED AUGUST 2006

Table 3. Status Detect and Operating Modes Descriptions

Mode Characteristics Conditions

Shutdown Mode Least amount of power consumption

off); All outputs are high-impedance

Standby Mode Low power consumption (only clock activity circuit active; PLL TXEN is high; PCLK input signal is missing or

is disabled to conserve power); All outputs are inactive high-impedance

Acquire Mode PLL tries to achieve lock; All outputs are high-impedance TXEN is high; PCLK input monitor detected input

Transmit Mode Data transfer (normal operation); Transmitter serializes data TXEN is high and PLL is locked to incoming clock

and transmits data on serial output; unused outputs remain high-impedance

(1) In Shutdown Mode, all SN65LVDS301 internal switching circuits (e.g., PLL, serializer, etc.) are turned off to minimize power

consumption. The input stage of any input pin remains active.

(2) Leaving inputs unconnected can cause random noise to toggle the input stage and potentially harm the device. All inputs must be tied to

a valid logic level VILor VIHduring Shutdown or Standby Mode.

(1)

(most circuitry turned TXEN is low

activity

Operating Mode Transitions

MODE TRANSITION USE CASE TRANSITION SPECIFICS

Shutdown → Standby Drive TXEN high to enable 1. TXEN high > 10 µ s

Standby → Acquire Transmitter activity detected 1. PCLK input monitor detects clock input activity;

Acquire → Transmit Link is ready to transfer data 1. PLL is active and approaches lock

Transmit → Standby Request Transmitter to enter 1. PCLK Input monitor detects missing PCLK

Transmit/Standby → Turn off Transmitter 1. TXEN pulled low for longer than 10us Shutdown

transmitter

Standby mode by stopping PCLK

2. Transmitter enters standby mode a. All outputs are high-impedance b. Transmitter turns on clock input monitor

2. Outputs remain high-impedance;

3. PLL circuit is enabled

2. PLL achieved lock within 2 ms

3. Parallel Data input latches into shift register

4. CLK output turns on

5. selected Data outputs turn on and send out first serial data bit

2. Transmitter indicates standby, putting all outputs into high-impedance;

3. PLL shuts down;

4. PCLK activity input monitor remains active

2. Transmitter indicates standby, putting output CLK+ and CLK– into high-impedance state;

3. Transmitter puts all other outputs into high-impedance state

4. Most IC circuitry is shut down for least power consumption

(1) (2)

(2)

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SN65LVDS301

SLLS681C – FEBRUARY 2006 – REVISED AUGUST 2006

PART NUMBER PACKAGE SHIPPING METHOD

SN65LVDS301ZQE Tray

SN65LVDS301ZQER Reel

ORDERING INFORMATION

ZQE

ABSOLUTE MAXIMUM RATINGS

(1)

over operating free-air temperature range (unless otherwise noted)

VALUE UNIT

Supply voltage range, V Voltage range at any input When V

or output terminal

Electrostatic discharge Charged-Device Mode

(2)

, V

When V Human Body Model

Machine Model

, V

DDPLLA

DDx DDx

, V

DDPLLD

DDLVDS

> 0 V -0.5 to 2.175 V

≤ 0 V -0.5 to V

(3)

(all Pins) ± 3 kV

(4)

l (all Pins) ± 500 V

(5)

(all pins) ± 200

-0.3 to 2.175 V

+ 2.175 V

Continuous power dissipation See Dissipation Rating Table

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to the GND terminals. (3) In accordance with JEDEC Standard 22, Test Method A114-A. (4) In accordance with JEDEC Standard 22, Test Method C101. (5) In accordance with JEDEC Standard 22, Test Method A115-A

DISSIPATION RATINGS

PACKAGE TA< 25 ° C

ZQE Low-K

CIRCUIT DERATING FACTOR

BOARD MODEL ABOVE TA= 25 ° C POWER RATING

(2)

592 mW 7.407 mW/ ° C 148 mW

(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. (2) In accordance with the Low-K thermal metric definitions of EIA/JESD51-2.

(1)

TA= 85 ° C

THERMAL CHARACTERISTICS

PARAMETER TEST CONDITIONS VALUE UNIT

Typical V

Device Power Dissipation

Maximum V

= 1.8 V, TA= 25 ° C mW

DDx

= 1.95 V, TA= –40 ° C mW

DDx

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PCLK at 4 MHz 14.4 PCLK at 65 MHz 44.5 PCLK at 4 MHz 22.3 PCLK=65 MHz 71.8

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