Texas Instruments SN65LVDS1050PW, SN65LVDS1050PWR Datasheet

SN65LVDS1050

HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS

SLLS343A – APRIL 1999 – REVISED MARCH 2000

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Typically Meets or Exceeds ANSI
TIA/EIA-644-1995 Standard

D

Operates From a Single 2.4-V to 3.6-V
Supply

D

Signaling Rates up to 400 Mbit/s

D

Bus-T erminal ESD Exceeds 12 kV

D

Low-Voltage Differential Signaling With
Typical Output Voltages of 285 mV and a
100 Ω Load

D

Propagation Delay Times
– Driver: 1.7 ns Typ
– Receiver: 3.7 ns Typ

D

Power Dissipation at 200 MHz
– Driver: 25 mW Typical
– Receiver: 60 mW Typical

D

LVTTL Input Levels Are 5 V Tolerant

D

Driver Is High Impedance When Disabled or
With VCC < 1.5 V

D

Receiver Has Open-Circuit Fail Safe

D

Available in Thin Shink Outline Packaging
With 20-mil Lead Pitch

description

The SN65LVDS1050 is similar to the
SN65LVDS050 except that it is characterized for
operation with a lower supply voltage range and
packaged in the thin shrink outline package for
portable battery-powered applications.

The differential line drivers and receivers use
low-voltage differential signaling (LVDS) to
achieve signaling rates as high as 400 Mbps. The
drivers provide a minimum differential output
voltage magnitude of 247 mV into a 100-Ω load
and receipt of 100-mV signals with up to 1 V of
ground potential difference between a transmitter
and receiver.

The intended application of this device and signaling technique is for point-to-point baseband data transmission
over controlled impedance media of approximately 100-Ω characteristic impedance. The transmission media
may be printed-circuit board traces, backplanes, or cables. Note: The ultimate rate and distance of data transfer
is dependent upon the attenuation characteristics of the media, the noise coupling to the environment and other
application-specific characteristics.

The SN65LVDS1050 is characterized for operation from –40°C to 85°C.

Copyright  2000, Texas Instruments Incorporated

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

9

1B
1A
1R

RE

2R
2A
2B

GND

V

CC

1D
1Y
1Z
DE
2Z
2Y
2D

SN65LVDS1050PW

(Marked as DL1050 or DLS1050)

(TOP VIEW)

2D

1D

1Y
1Z

2Y
2Z

DE

9

15

12

14
13

10
11

2R

1R

1A
1B

2A
2B

RE

5

3

4

2
1

6
7

DRIVER FUNCTION TABLE

RECEIVER FUNCTION TABLE

INPUTS OUTPUTS

INPUTS OUTPUT

D

X

DE Y

X

VID = VA – V

B

VID ≥ 100 mV

–100 MV < VID < 100 mV

VID ≤ –100 mV

Open

RE

R

L

Open

Z

L

L
L
H

H
?
L
H
Z

Z

LL
HHHH

L

H

Z

L

HHL

H = high level, L = low level, Z = high impedance,
X = don’t care

H = high level, L = low level, Z = high impedance,
X = don’t care

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN65LVDS1050
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS

SLLS343A – APRIL 1999 – REVISED MARCH 2000

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

equivalent input and output schematic diagrams

300 kΩ

50 Ω

V

CC

7 V

D or RE

Input

300 kΩ

50 Ω

V

CC

7 V

DE

Input

5 Ω

10 kΩ

7 V

Y or Z
Output

V

CC

7 V

V

CC

7 V

R Output

V

CC

5 Ω

B InputA Input

300 kΩ300 kΩ

7 V

SN65LVDS1050

HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS

SLLS343A – APRIL 1999 – REVISED MARCH 2000

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Supply voltage range, VCC (see Note 1) –0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range (D, R, DE, RE) –0.5 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range (Y, Z, A, and B) –0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Electrostatic discharge: Y, Z, A, B , and GND (see Note 2) CLass 3, A:12 kV, B:600 V. . . . . . . . . . . . . . . . . .

All terminals Class 3, A:7 kV, B:500 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 250°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values, except differential I/O bus voltages are with respect to network ground terminal.

2. Tested in accordance with MIL-STD-883C Method 3015.7.

DISSIPATION RATING T ABLE

PACKAGE

TA ≤ 25°C

POWER RATING

DERATING FACTOR

ABOVE TA = 25°C

TA = 85°C

POWER RATING

PW 774 mW 6.2 mW/°C 402 mW

recommended operating conditions (see Note 3)

MIN NOM MAX UNIT

Supply voltage, V

CC

2.4 2.7 3.6 V

High-level input voltage, V

IH

2 V

Low-level input voltage, V

IL

0.8 V

Magnitude of differential input voltage, VID 0.1 0.6 V

Common–mode input voltage, VIC (see Figure 8)

0

2.4

*

Ť

V

ID

Ť

2

V

g

IC

(g)

VCC–0.8

Operating free–air temperature, T

A

–40 85 °C

NOTE 3: The common-mode input voltage, VIC, is not fully 644 compliant when VCC = 2.4 V.

SN65LVDS1050
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS

SLLS343A – APRIL 1999 – REVISED MARCH 2000

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

device electrical characteristics over recommended operating conditions (unless otherwise
noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

Driver and receiver enabled, No receiver load,
Driver RL = 100 Ω

12 20

I

Supply current

Driver enabled, Receiver disabled, RL = 100 Ω

10 16

mA

ICCSu ly current

Driver disabled, Receiver enabled, No load 3 6

mA

Disabled 0.5 1

†

All typical values are at 25°C and with a 2.7-V supply.

driver electrical characteristics over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VOD Differential output voltage magnitude

247 285 454

∆VOD

Change in differential output voltage magnitude between logic
states

R

L

=

100Ω

,

See Fi gure 1 and Figure 2

–50 50

mV

V

OC(SS)

Steady-state common-mode output voltage 1.125 1.375 V

∆V

OC(SS)

Change in steady-state common-mode output voltage between
logic states

See Fi gure 3

–50 50 mV

V

OC(PP)

Peak-to-peak common-mode output voltage 50 150 mV

p

DE

–0.5 –20

IIHHigh-level input current

D

V

IH

=

5 V

2 20

µ

A

p

DE

–0.5 –10

IILLow-level input current

D

V

IL

= 0.8

V

2 20

µ

A

p

VOY or VOZ = 0 V 3 10

IOSShort-circuit output current

VOD = 0 V 3 10

mA

p

p

VOD = 600 mV ±1

IOZHigh-impedance output current

VO = 0 V or V

CC

±1

µ

A

I

O(OFF)

Power-off output current VCC = 0 V, VO = 3.6 V ±1 µA

C

IN

Input capacitance 3 pF

receiver electrical characteristics over recommended operating conditions (unless otherwise
noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

V

ITH+

Positive-going differential input voltage threshold

100

V

ITH–

Negative-going differential input voltage threshold

See Figure 5

–100

mV

V

OH

High-level output voltage IOH = –8 mA 2 V

V

OL

Low-level output voltage IOL = 8 mA 0.4 V

p

p

VI = 0 –2 –20

IIInput current (A or B inputs)

VI = 2.4 V –1.2

µ

A

I

I(OFF)

Power-off input current (A or B inputs) VCC = 0 ±20 µA

I

IH

High-level input current (enables) VIH = 5 V ±10 µA

I

IL

Low-level input current (enables) VIL = 0.8 V ±10 µA

I

OZ

High-impedance output current VO = 0 or 5 V ±10 µA

†

All typical values are at 25°C and with a 2.7-V supply.

SN65LVDS1050

HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS

SLLS343A – APRIL 1999 – REVISED MARCH 2000

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

driver switching characteristics over recommended operating conditions (unless otherwise
noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

t

PLH

Propagation delay time, low-to-high-level output 1.7 2.7 ns

t

PHL

Propagation delay time, high-to-low-level output 1.7 3 ns

t

r

Differential output signal rise time

RL = 100Ω,

p

0.8 1 ns

t

f

Differential output signal fall time

C

L

= 10 pF,

See

Figure 2

0.8 1 ns

t

sk(p)

Pulse skew (|t

pHL

– t

pLH

|)

See Figure 2

300 ps

t

sk(o)

Channel-to-channel output skew

‡

150 ps

t

PZH

Propagation delay time, high-impedance-to-high-level output 7.8 10 ns

t

PZL

Propagation delay time, high-impedance-to-low-level output

7.3 10 ns

t

PHZ

Propagation delay time, high-level-to-high-impedance output

See Figure 4

5.2 10 ns

t

pLZ

Propagation delay time, low-level-to-high-impedance output 6.6 10 ns

†

All typical values are at 25°C and with a 2.7-V supply.

‡

t

sk(o)

is the maximum delay time difference between drivers on the same device.

receiver switching characteristics over recommended operating conditions (unless otherwise
noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

t

PLH

Propagation delay time, low-to-high-level output 3.7 5.2 ns

t

PHL

Propagation delay time, high-to-low-level output

3.7 4.5 ns

t

sk(p)

Pulse skew (|t

pHL

– t

pLH

|)

CL = 10 pF,

0.3 ns

t

r

Output signal rise time

See Figure 6

0.8 1.5 ns

t

f

Output signal fall time 0.8 1.5 ns

t

PZH

Propagation delay time, high-level-to-high-impedance output 5.4 ns

t

PZL

Propagation delay time, low-level-to-low-impedance output

6.3 ns

t

PHZ

Propagation delay time, high-impedance-to-high-level output

See Figure 7

6.1 ns

t

PLZ

Propagation delay time, low-impedance-to-high-level output 6.9 ns

†

All typical values are at 25°C and with a 2.7-V supply.

PARAMETER MEASUREMENT INFORMATION

driver

V

OD

V

OZ

V

OY

V

OC

V

I

I

OY

I

OZ

I

I

A

Z

Y

VOY)

V

OZ

2

Driver Enable

Figure 1. Driver Voltage and Current Definitions

SN65LVDS1050
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS

SLLS343A – APRIL 1999 – REVISED MARCH 2000

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

driver (continued)

2 V

1.4 V

0.8 V

100%
80%

20%
0%

0 V

V

OD(H)

V

OD(L)

Output

Input

V

OD

Z

Y

Input

100 Ω
±1%

CL = 10 pF
(2 Places)

t

PHL

t

PLH

t

f

t

r

Driver Enable

NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,

pulse width = 10 ± 0.2 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.

Figure 2. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal

V

OC

Z

Y

Input

CL = 10 pF
(2 Places)

3 V

0 V

V

OC(PP)

V

OC(SS)

V

OC

49.9 Ω, ±1% (2 Places)

Driver Enable

NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,

pulse width = 10 ± 0.2 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T . The measurement of V

OC(PP)

is made on test equipment with a –3 dB bandwidth of at least 300 MHz.

Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage