Texas Instruments SN65LVDS051DR, SN65LVDS180DR, SN65LVDS050D, SN65LVDS050DR, SN65LVDS051D Datasheet

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SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
D
Meets or Exceeds the Requirements of ANSI TIA/EIA-644-1995 Standard
D
Signaling Rates up to 400 Mbit/s
D
Bus-T erminal ESD Exceeds 12 kV
D
Operates from a Single 3.3-V Supply
D
Low-Voltage Differential Signaling With Typical Output Voltages of 350 mV and a 100 Load
D
Propagation Delay Times – Driver: 1.7 ns Typ – Receiver: 3.7 ns Typ
D
Power Dissipation at 200 MHz – Driver: 25 mW Typical – Receiver: 60 mW Typical
D
LVTTL Input Levels are 5 V Tolerant
D
Driver is High Impedance When Disabled or With V
D
Receiver has Open-Circuit Fail Safe
D
Surface-Mount Packaging – D Package (SOIC) – DGK Package (MSOP) (’LVDS79 Only)
description
The SN65LVDS179, SN65LVDS180, SN65L VDS050, and SN65LVDS051 are dif feren­tial line drivers and receivers that use low-voltage differential signaling (LVDS) to achieve signaling rates as high as 400 Mbps. The TIA/EIA-644 standard compliant electrical interface provides a minimum differential output voltage magnitude of 247 mV into a 100 load and receipt of 100 mV signals with up to 1 V of ground potential difference between a transmitter and receiver.
The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 Ω characteristic impedance. The transmission media may be printed-circuit board traces, backplanes, or cables. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other application specific characteristics).
< 1.5 V
CC
SLLS301G – APRIL 1998 – REVISED MARCH 2000
SN65LVDS179D (Marked as DL179 or LVD179)
SN65LVDS179DGK (Marked as S79)
SN65LVDS180D (Marked as LVDS180)
SN65LVDS050D (Marked as LVDS050)
SN65LVDS051D (Marked as LVDS051)
V
CC
GND
NC
RE DE
GND GND
1B 1A 1R
RE
2R 2A 2B
GND
1B 1A 1R
1DE
2R 2A 2B
GND
(TOP VIEW)
1
R
2
D
3 4
(TOP VIEW)
1
R
2 3 4
D
5 6 7
(TOP VIEW)
1 2 3 4 5 6 7 8
(TOP VIEW)
1 2 3 4 5 6 7 8
14 13 12 11 10
16 15 14 13 12 11 10
16 15 14 13 12 11 10
A
8
B
7
Z
6 5
Y
V
CC
V
CC
A B Z Y
9
NC
8
V
CC
1D 1Y
D
R
D
DE RE
R
1D
DE
2D
1Z DE
1R
2Z 2Y
9
2D
V
CC
1D 1Y
RE
2R
1D
1DE
1R
1Z 2DE 2Z 2Y
9
2D
2D
2DE
2R
15
12
15
12
3
2
5 4
3 2
9
3
4 5
4 3
9
5
5
Y
6
Z
8
A
7
B
9
Y
10
Z
12
A
11
B
14
1Y
13
1Z
10
2Y
11
2Z
2
1A
1
1B
6
2A
7
2B
14
1Y
13
1Z
2
1A
1
1B
10
2Y
11
2Z
6
2A
7
2B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright  2000, Texas Instruments Incorporated
1
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
40°C to 85°C
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G – APRIL 1998 – REVISED MARCH 2000
description (continued)
AVAILABLE OPTIONS
PACKAGE
T
A
°
°
The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other application specific characteristics.
The SN65L VDS179, SN65L VDS180, SN65L VDS050, and SN65L VDS051 are characterized for operation from –40°C to 85°C.
SMALL OUTLINE
(D)
SN65LVDS050D — SN65LVDS051D — SN65LVDS179D SN65LVDS179DGK SN65LVDS180D
SMALL OUTLINE
(DGK)
NOTE:
Function Tables
SN65LVDS179 RECEIVER
INPUTS
VID = VA – V
VID 100 mV H
–100 MV < VID < 100 mV ?
VID –100 mV L
Open H
H = high level, L = low level, ? = indeterminate
SN65LVDS179 DRIVER
INPUT
D Y Z
L L H
H H L
Open L H
H = high level, L = low level
SN65LVDS180, SN65LVDS050, and
SN65LVDS051 RECEIVER
INPUTS
VID = VA – V
VID 100 mV L H
–100 MV < VID < 100 mV L ?
VID –100 mV L L
Open L H
X H Z
H = high level, L = low level, Z = high impedance, X = don’t care
B
OUTPUTS
B
OUTPUT
R
OUTPUT
RE R
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SN65LVDS180, SN65LVDS050, and
SN65LVDS051 DRIVER
INPUTS OUTPUTS
D DE Y Z
L H L H
H H H L
Open H L H
X L Z Z
H = high level, L = low level, Z = high impedance, X = don’t care
equivalent input and output schematic diagrams
V
CC
300 k
D or RE
Input
7 V
50
300 k
DE
50
Input
7 V
SLLS301G – APRIL 1998 – REVISED MARCH 2000
V
CC
V
CC
10 k
5
Y or Z Output
7 V
7 V
V
CC
300 k300 k
B InputA Input
7 V
V
CC
5
R Output
7 V
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
SN65LVDS180
mA
S
current
SN65LVDS050
mA
SN65LVDS051
mA
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G – APRIL 1998 – REVISED MARCH 2000
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, VCC (see Note 1) –0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range (D, R, DE, RE) –0.5 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrostatic discharge: Y, Z, A, B , and GND (see Note 2) CLass 3, A:12 kV, B:600 V. . . . . . . . . . . . . . . . . .
All Class 3, A:7 kV, B:500 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous power dissipation see dissipation rating table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 250°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages are with respect to network ground terminal.
2. Tested in accordance with MIL-STD-883C Method 3015.7.
DISSIPATION RATING TABLE
PACKAGE
D8 725 mW 5.8 mW/°C 377 mW
D14 or D16 950 mW 7.8 mW/°C 494 mW
DGK 424 mW 3.4 mW/°C 220 mW
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
TA 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 85°C
POWER RATING
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, V High-level input voltage, V Low-level input voltage, V Magnitude of differential input voltage, VID 0.1 0.6 V
Common–mode input voltage, VIC (see Figure 6)
Operating free–air temperature, T
CC
IH
IL
A
3 3.3 3.6 V 2 V
0.8 V
Ť
Ť
V
ID
2
–40 85 °C
2.4
*
VCC–0.8
Ť
V
ID
2
Ť
V
device electrical characteristics over recommended operating conditions (unless otherwise noted)
I
4
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
SN65LVDS179 No receiver load, Driver RL = 100 9 12 mA
Driver and receiver enabled, No receiver load, Driver RL = 100 9 12 Driver enabled, Receiver disabled, RL = 100 5 7 Driver disabled, Receiver enabled, No load 1.5 2
upply
CC
All typical values are at 25°C and with a 3.3-V supply.
Disabled 0.5 1 Drivers and receivers enabled, No receiver loads, Driver RL = 100 12 20 Drivers enabled, Receivers disabled, RL = 100 10 16 Drivers disabled, Receivers enabled, No loads 3 6 Disabled 0.5 1 Drivers enabled, No receiver loads, Driver RL = 100 12 20 Drivers disabled, No loads 3 6
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
R
100
IIHHigh-level input current
V
V
A
IILLow-level input current
V
V
A
IOSShort-circuit output current
mA
IOZHigh-impedance output current
A
See Figure 5 and Table 1
mV
IIInput current (A or B inputs)
A
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G – APRIL 1998 – REVISED MARCH 2000
driver electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOD Differential output voltage magnitude
VOD V
OC(SS)
V
OC(SS)
V
OC(PP)
I
O(OFF)
C
IN
Change in differential output voltage magnitude between logic states
Steady-state common-mode output voltage 1.125 1.2 1.375 V Change in steady-state common-mode output voltage between
logic states Peak-to-peak common-mode output voltage 50 150 mV
p
p
p
p
Power-off output current VCC = 0 V, VO = 3.6 V ±1 µA Input capacitance 3 pF
p
=
L
See Figure 1 and Figure 2
See Figure 3
DE
DE
IH
D
IL
D
VOY or VOZ = 0 V 3 10 VOD = 0 V 3 10 VOD = 600 mV ±1 VO = 0 V or V
,
= 5
= 0.8
CC
247 340 454
±1
mV
µ
µ
µ
–50 50
–50 50 mV
–0.5 –20
2 20
–0.5 –10
2 10
receiver electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
ITH+
V
ITH–
V
OH
V
OL
I
I(OFF)
I
IH
I
IL
I
OZ
C
I
All typical values are at 25°C and with a 3.3-V supply.
Positive-going differential input voltage threshold Negative-going differential input voltage threshold High-level output voltage IOH = –8 mA 2.4 V Low-level output voltage IOL = 8 mA 0.4 V
p
Power-off input current (A or B inputs) VCC = 0 ±20 µA High-level input current (enables) VIH = 5 V ±10 µA Low-level input current (enables) VIL = 0.8 V ±10 µA High-impedance output current VO = 0 or 5 V ±10 µA
Input capacitance 5 pF
p
VI = 0 –2 –11 –20 VI = 2.4 V –1.2 –3
–100
100
µ
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5
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051
C See
6
See Figure 6
See Figure 7
See Figure 7
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SLLS301G – APRIL 1998 – REVISED MARCH 2000
driver switching characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
t
PLH
t
PHL
t
r
t
f
t
sk(p)
t
sk(o)
t
PZH
t
PZL
t
PHZ
t
pLZ
All typical values are at 25°C and with a 3.3-V.
t
sk(p)
§
t
sk(o)
t
sk(pp)
operate with the same supply voltages, same temperature, and have identical packages and test circuits.
Propagation delay time, low-to-high-level output 1.7 2.7 ns Propagation delay time, high-to-low-level output 1.7 2.7 ns Differential output signal rise time Differential output signal fall time Pulse skew (|t Channel-to-channel output skew Propagation delay time, high-impedance-to-high-level output 4.3 10 ns Propagation delay time, high-impedance-to-low-level output Propagation delay time, high-level-to-high-impedance output Propagation delay time, low-level-to-high-impedance output 3.4 10 ns
is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output. is the magnitude of the time difference between the outputs of a single device with all of their inputs connected together.
is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both devices
pHL
– t
pLH
|)
§
RL = 100Ω,
= 10 pF,
L
Figure
p
0.8 1 ns
0.8 1 ns 300 ps 150 ps
4.6 10 ns
3.1 10 ns
receiver switching characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
t
PLH
t
PHL
t
sk(p)
t
r
t
f
t
PZH
t
PZL
t
PHZ
t
PLZ
All typical values are at 25°C and with a 3.3-V.
t
sk(p)
§
t
sk(o)
t
sk(pp)
operate with the same supply voltages, same temperature, and have identical packages and test circuits.
Propagation delay time, low-to-high-level output 3.7 4.5 ns Propagation delay time, high-to-low-level output 3.7 4.5 ns Pulse skew (|t Output signal rise time 0.7 1.5 ns Output signal fall time 0.9 1.5 ns Propagation delay time, high-level-to-high-impedance output 2.5 ns Propagation delay time, low-level-to-low-impedance output Propagation delay time, high-impedance-to-high-level output Propagation delay time, low-impedance-to-high-level output 4 ns
is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output. is the magnitude of the time difference between the outputs of a single device with all of their inputs connected together.
is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both devices
pHL
– t
pLH
|)
CL = 10 pF, See Figure 6
0.3 ns
2.5 ns
7 ns
6
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