Datasheet SN65LBC173D, SN65LBC173DR, SN65LBC173N, SN75LBC173D, SN75LBC173DR Datasheet (Texas Instruments)

SN65LBC173, SN75LBC173

QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS

SLLS170C – OCTOBER 1993 – REVISED JANUARY 2000

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Meets or Exceeds the Requirements of
ANSI Standards EIA/TIA-422-B,
EIA/TIA-423-B, RS-485, and ITU
Recommendations V.10 and V.11.

D

Designed to Operate With Pulse Durations
as Short as 20 ns

D

Designed for Multipoint Bus Transmission
on Long Bus Lines in Noisy Environments

D

Input Sensitivity . . . ±200 mV

D

Low-Power Consumption . . . 20 mA Max

D

Open-Circuit Fail-Safe Design

D

Pin Compatible With SN75173 and
AM26LS32

description

The SN65LBC173 and SN75LBC173 are monolithic quadruple differential line receivers with 3-state outputs.
Both are designed to meet the requirements of the ANSI standards EIA/TIA-422-B, EIA/TIA-423-B, RS-485,
and ITU Recommendations V .10 and V .1 1. The devices are optimized for balanced multipoint bus transmission
at data rates up to and exceeding 10 million bits per second. The four receivers share two ORed enable inputs,
one active when high, the other active when low.

Each receiver features high input impedance, input hysteresis for increased noise immunity, and input
sensitivity of ±200 mV over a common-mode input voltage range of 12 V to –7 V . Fail-safe design ensures that
if the inputs are open circuited, the output is always high. Both devices are designed using the T exas Instruments
proprietary LinBiCMOS technology that provides low power consumption, high switching speeds, and
robustness.

These devices offer optimum performance when used with the SN75LBC172 or SN75LBC174 quadruple line
drivers. The SN65LBC173 and SN75LBC173 are available in the 16-pin DIP (N) and SOIC (D) packages.

The SN65LBC173 is characterized over the industrial temperature range of –40°C to 85°C. The SN75LBC173
is characterized for operation over the commercial temperature range of 0°C to 70°C.

FUNCTION TABLE

(each receiver)

DIFFERENTIAL INPUTS

ENABLES

OUTPUT

A–B

G G

Y

VID ≥ 0.2 V

H
X

X
L

H
H

–0.2 V < VID < 0.2 V

H
X

X
L

?
?

VID ≤ –0.2 V

H
X

X
L

L
L

X L H Z

Open Circuit

H
X

X
L

H
H

H = high level, L = low level, X = irrelevant,
Z = high impedance (off), ? = indeterminate

LinBiCMOS is a trademark of Texas Instruments Incorporated.

Copyright  2000, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

9

1B
1A
1Y

G
2Y
2A
2B

GND

V

CC

4B
4A
4Y
G
3Y
3A
3B

D OR N PACKAGE

(TOP VIEW)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN65LBC173, SN75LBC173
QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS

SLLS170C – OCTOBER 1993 – REVISED JANUARY 2000

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic symbol

†

4B

4A

3B

3A

2B

2A

1B

1A

G

G

4Y

3Y

2Y

1Y

13

11

5

3

15

14

9

10

7

6

1

2

12

4

≥ 1

†

This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.

logic diagram (positive logic)

4Y

3Y

2Y

1Y

13

11

5

3

15

14

9

10

7

6

1

2

12

4

4B

4A

3B

3A

2B

2A

1B

1A

G

G

schematics of inputs and outputs

TYPICAL OF ALL OUTPUTS

V

CC

Y Output

EQUIVALENT OF A AND B INPUTS

12 kΩ

3 kΩ

18 kΩ

1 kΩ

V

CC

Input

100 kΩ
A Only

100 kΩ
B Only

Input

V

CC

Receiver

TYPICAL OF G AND G INPUTS

SN65LBC173, SN75LBC173

QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS

SLLS170C – OCTOBER 1993 – REVISED JANUARY 2000

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, VCC (see Note 1) –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage, VI (A or B inputs) ±25 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Differential input voltage, VID (see Note 2) ±25 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range at Y, G, G

–0.3 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA: SN65LBC173 –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN75LBC173 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values are with respect to GND.

2. Differential input voltage is measured at the noninverting input with respect to the corresponding inverting input.

DISSIPATION RATING TABLE

PACKAGE

TA ≤ 25°C

POWER RATING

DERATING FACTOR

ABOVE TA = 25°C

TA = 70°C

POWER RATING

TA = 85°C

POWER RATING

D 1100 mW 8.7 mW/°C 708 mW 578 mW
N 1150 mW 9.2 mW/°C 736 mW 598 mW

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, V

CC

4.75 5 5.25 V

Common-mode input voltage, V

IC

–7 12 V

Differential input voltage, V

ID

±6 V

High-level input voltage, V

IH

p

2 V

Low-level input voltage, V

IL

G inputs

0.8 V

High-level output current, I

OH

–8 mA

Low-level output current, I

OL

16 mA

p

p

SN65LBC173 –40 85

°

Operating free-air temperature, T

A

SN75LBC173 0 70

°C

SN65LBC173, SN75LBC173
QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS

SLLS170C – OCTOBER 1993 – REVISED JANUARY 2000

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

V

IT+

Positive-going input threshold voltage IO = –8 mA 0.2 V

V

IT–

Negative-going input threshold voltage IO = 16 mA –0.2 V

V

hys

Hysteresis voltage (V

IT+

– V

IT–

) 45 mV

V

IK

Enable input clamp voltage II = –18 mA –0.9 –1.5 V

V

OH

High-level output voltage VID = 200 mV , IOH = –8 mA 3.5 4.5 V

V

OL

Low-level output voltage VID = –200 mV, IOL = 16 mA 0.3 0.5 V

I

OZ

High-impedance-state output current VO = 0 V to V

CC

±20 µA

VIH = 12 V, VCC = 5 V , Other inputs at 0 V 0.7 1 mA

p

p

VIH = 12 V, VCC = 0 V , Other inputs at 0 V 0.8 1 mA

IIBus input current

A or B inputs

VIH = –7 V , VCC = 5 V , Other inputs at 0 V –0.5 –0.8 mA
VIH = –7 V , VCC = 0 V , Other inputs at 0 V –0.4 –0.8 mA

I

IH

High-level input current VIH = 5 V ±20 µA

I

IL

Low-level input current VIL = 0 V –20 µA

I

OS

Short-circuit output current VO = 0 –80 –120 mA

pp

Outputs enabled, IO = 0, VID = 5 V 11 20

ICCSupply current

Outputs disabled 0.9 1.4

mA

†

All typical values are at VCC = 5 V and TA = 25°C.

switching characteristics, VCC = 5 V, CL = 15 pF, TA = 25°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t

PHL

Propagation delay time, high- to low-level output

11 22 30 ns

t

PLH

Propagation delay time, low- to high-level output

V

ID

= –

1.5 V to 1.5 V

,

See Figure 1

11 22 30 ns

t

PZH

Output enable time to high level See Figure 2 17 30 ns

t

PZL

Output enable time to low level See Figure 3 18 30 ns

t

PHZ

Output disable time from high level See Figure 2 35 45 ns

t

PLZ

Output disable time from low level See Figure 3 25 40 ns

t

sk(p)

Pulse skew (|t

PHL

– t

PLH

|) See Figure 2 0.5 6 ns

t

t

Transition time See Figure 1 5 10 ns

SN65LBC173, SN75LBC173

QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS

SLLS170C – OCTOBER 1993 – REVISED JANUARY 2000

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

V

OL

V

OH

– 1.5 V

1.5 V

Output

Input

1.3 V1.3 V

t

PHL

t

PLH

0 V0 V

2 V

(see Note A)

Generator

Output

(see Note B)

CL = 15 pF

50 Ω

TEST CIRCUIT

VOLTAGE WAVEFORMS

t

t

t

t

90%

10%

Figure 1. tpd and tt Test Circuit and Voltage Waveforms

(see Note D)

0 V

S1 Open

S1 Closed

1.3 V1.3 V

t

PHZ

t

PZH

0.5 V

See Note C

V

CC

2 kΩ

S1

5 kΩ

1.5 V

CL = 15 pF
(see Note B)

Output

Generator

(see Note A)

2 V

1.3 V

Input

Output

3 V

0 V

V

OH

≈ 1.4 V

50 Ω

TEST CIRCUIT

VOLTAGE WAVEFORMS

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle = 50%, tr ≤ 6 ns,

tf ≤ 6 ns, ZO = 50 Ω.
B. CL includes probe and jig capacitance.
C. All diodes are 1N916 or equivalent.
D. To test the active-low enable G

, ground G and apply an inverted input waveform to G.

Figure 2. t

PHZ

and t

PZH

Test Circuit and Voltage Waveforms

SN65LBC173, SN75LBC173
QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS

SLLS170C – OCTOBER 1993 – REVISED JANUARY 2000

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

S2

0 V

3 V

S2 Closed

t

PLZ

S2 Open

t

PZL

V

OL

Output

Input

1.3 V

2 V

(see Note A)

Generator

Output

(see Note B)

CL = 15 pF

1.5 V

See Note C

0.5 V

1.3 V 1.3 V

(see Note D)

50 Ω

5 kΩ

2 kΩ

V

CC

≈ 1.4 V

TEST CIRCUIT

VOLTAGE WAVEFORMS

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle = 50%, tr ≤ 6 ns,

tf ≤ 6 ns, ZO = 50 Ω.
B. CL includes probe and jig capacitance.
C. All diodes are 1N916 or equivalent.
D. To test the active-low enable G

, ground G and apply an inverted input waveform to G.

Figure 3. t

PZL

and t

PLZ

Test Circuit and Voltage Waveforms

TYPICAL CHARACTERISTICS

Figure 4

1.5

1

0.5

0

01020304050

– Output Voltage – V

2

2.5

OUTPUT VOLTAGE

vs

DIFFERENTIAL INPUT VOLTAGE

3

60 70 80

90 100

3.5

4

4.5

V

O

VID – Differential Input Voltage – mV

VCC = 5 V
TA = 25°C

V

IC

= 0 V

V

IC

= 12 V

V

IC

= 0 V

V

IC

= 12 V

V

IC

= – 7 V

V

IC

= – 7 V

Figure 5

1.5
1

0.5
0

0 – 4 – 8 – 12 – 16 – 20

– High-Level Output Voltage – V

2

2.5

HIGH-LEVEL OUTPUT VOLTAGE

vs

HIGH-LEVEL OUTPUT CURRENT

3

– 24 – 28 – 32 – 36 – 40

3.5

4

4.5

V

OH

IOH – High-Level Output Current – mA

5

5.5

VCC = 4.75 V

VCC = 5.25 V

VCC = 5 V

VID = 0.2 V
TA = 25°C

SN65LBC173, SN75LBC173

QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS

SLLS170C – OCTOBER 1993 – REVISED JANUARY 2000

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 6

180
120

60

0

0 3 6 9 12 15

– Low-Level Output Voltage – mV

240

300

LOW-LEVEL OUTPUT VOLTAGE

vs

LOW-LEVEL OUTPUT CURRENT

360

18 21 24 27 30

420

480

540

V

OL

IOL – Low-Level Output Current – mA

600

660

TA = 25°C
VCC = 5 V
VID = 200 mV

Figure 7

6

4

2

0

10 K 100 K 2 M

– Average Supply Current – mA

8

10

AVERAGE SUPPLY CURRENT

vs

FREQUENCY

12

10 M 100 M

14

I

CC

f – Frequency – Hz

TA = 25°C
VCC = 5 V

Figure 8

– 0.4
– 0.6

– 0.8

– 1

– 8 – 6 – 4 – 2 0 2

– Input Current – mA

– 0.2

0

BUS

INPUT CURRENT

vs

INPUT VOLTAGE

(COMPLEMENTARY INPUT AT 0 V)

0.2

468

10 12

0.4

0.6

0.8

I

I

VI – Input Voltage – V

1

TA = 25°C
VCC = 5 V

The shaded region of this graph represents
more than 1 unit load per RS-485.

Figure 9

23.5

23

22.5

22

– 40 – 20 0 20 40 60

Propagation Delay Time – ns

24

24.5

PROPAGATION DELAY TIME

vs

FREE-AIR TEMPERATURE

80 100

TA – Free-Air Temperature – °C

t

PHL

t

PLH

VCC = 5 V
CL = 15 pF
VIO = ±1.5 V

SN65LBC173, SN75LBC173
QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS

SLLS170C – OCTOBER 1993 – REVISED JANUARY 2000

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

4040047/D 10/96

0.228 (5,80)

0.244 (6,20)

0.069 (1,75) MAX

0.010 (0,25)

0.004 (0,10)

1

14

0.014 (0,35)

0.020 (0,51)

A

0.157 (4,00)

0.150 (3,81)

7

8

0.044 (1,12)

0.016 (0,40)

Seating Plane

0.010 (0,25)

PINS **

0.008 (0,20) NOM

A MIN

A MAX

DIM

Gage Plane

0.189

(4,80)

(5,00)

0.197

8

(8,55)

(8,75)

0.337

14

0.344

(9,80)

16

0.394

(10,00)

0.386

0.004 (0,10)

M

0.010 (0,25)

0.050 (1,27)

0°–8°

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012

SN65LBC173, SN75LBC173

QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVERS

SLLS170C – OCTOBER 1993 – REVISED JANUARY 2000

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE

20

0.975

(24,77)

0.940

(23,88)

18

0.920

0.850

14

0.775

0.745

(19,69)

(18,92)

16

0.775

(19,69)

(18,92)

0.745

A MIN

DIM

A MAX

PINS **

0.310 (7,87)

0.290 (7,37)

(23.37)

(21.59)

Seating Plane

0.010 (0,25) NOM

14/18 PIN ONL Y

4040049/C 08/95

9

8

0.070 (1,78) MAX

A

0.035 (0,89) MAX

0.020 (0,51) MIN

16

1

0.015 (0,38)

0.021 (0,53)

0.200 (5,08) MAX

0.125 (3,18) MIN

0.240 (6,10)

0.260 (6,60)

M

0.010 (0,25)

0.100 (2,54)

0°–15°

16 PIN SHOWN

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001.)

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
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Copyright  2000, Texas Instruments Incorporated