TEXAS INSTRUMENTS SN65HVD05, SN65HVD06, SN75HVD05, SN65HVD07, SN75HVD06 Technical data

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1
2
3
4

8
7
6
5

R
RE
DE

D

V

CC

B
A
GND

D OR P PACKAGE

(TOP VIEW)

1

2

3

4

6

7

A

B

R

RE

DE

D

LOGIC DIAGRAM

(POSITIVE LOGIC)

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

0 20 40 60 80 100 120

- Differential Output Voltage - V

DIFFERENTIAL OUTPUT VOLTAGE

vs

DIFFERENTIAL OUTPUT CURRENT

V

O

IOD - Differential Output Current - mA

60 Ω Load
Line

30 Ω Load
Line

TA = 25°C
DE at V

CC

D at V

CC

V

CC

= 5 V

查询SN65HVD07DG4供应商

HIGH OUTPUT RS-485 TRANSCEIVERS

FEATURES DESCRIPTION

• Minimum Differential Output Voltage of 2.5 V
Into a 54- Ω Load

• Open-Circuit, Short-Circuit, and Idle-Bus
Failsafe Receiver

• 1/8

• Bus-Pin ESD Protection Exceeds 16 kV HBM

• Driver Output Slew Rate Control Options

• Electrically Compatible With ANSI

• Low-Current Standby Mode . . . 1 µA Typical

• Glitch-Free Power-Up and Power-Down

• Pin Compatible With Industry Standard

APPLICATIONS

• Data Transmission Over Long or Lossy Lines

• Profibus Line Interface

• Industrial Process Control Networks

• Point-of-Sale (POS) Networks

• Electric Utility Metering

• Building Automation

• Digital Motor Control

th

Unit-Load Option Available (Up to 256

Nodes on the Bus)

TIA/EIA-485-A Standard

Protection for Hot-Plugging Applications

SN75176

or Electrically Noisy Environments

SN65HVD05 , , SN65HVD06
SN75HVD05 , SN65HVD07
SN75HVD06 , SN75HVD07

SLLS533D – MAY 2002 – REVISED JULY 2006

The SN65HVD05, SN75HVD05, SN65HVD06,
SN75HVD06, SN65HVD07, and SN75HVD07
combine a 3-state differential line driver and
differential line receiver. They are designed for
balanced data transmission and interoperate with
ANSI TIA/EIA-485-A and ISO 8482E
standard-compliant devices. The driver is designed
to provide a differential output voltage greater than
that required by these standards for increased noise
margin. The drivers and receivers have active-high
and active-low enables respectively, which can be
externally connected together to function as direction
control.

The driver differential outputs and receiver
differential inputs connect internally to form a
differential input/ output (I/O) bus port that is
designed to offer minimum loading to the bus
whenever the driver is disabled or not powered.
These devices feature wide positive and negative
common-mode voltage ranges, making them suitable
for party-line applications.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright © 2002–2006, Texas Instruments Incorporated

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SN65HVD05 , , SN65HVD06
SN75HVD05 , SN65HVD07
SN75HVD06 , SN75HVD07

SLLS533D – MAY 2002 – REVISED JULY 2006

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

SIGNALING UNIT

RATE LOAD

40 Mbps 1/2 No SN65HVD05D SN65HVD05P 65HVD05 VP05
10 Mbps 1/8 Yes 40°C to 85°C SN65HVD06D SN65HVD06P 65HVD06 VP06

1 Mbps 1/8 Yes SN65HVD07D SN65HVD07P 65HVD07 VP07
40 Mbps 1/2 No SN75HVD05D SN75HVD05P 75HVD05 VN05
10 Mbps 1/8 Yes 0°C to 70°C SN75HVD06D SN75HVD06P 75HVD06 VN06

1 Mbps 1/8 Yes SN75HVD07D SN75HVD07P 75HVD07 VN07

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com .

(2) The D package is available taped and reeled. Add an R suffix to the device type (i.e., SN65HVD05DR).

DRIVER

OUTPUT SLOPE T

CONTROL

A

PART NUMBER

(1)

MARKED AS

(2)

PLASTIC SMALL

DUAL-IN-LINE OUTLINE

PACKAGE IC (SOIC)

(PDIP) PACKAGE

PACKAGE DISSIPATION RATINGS

(See Figure 12 and Figure 13 )

PACKAGE

(2)

D

(3)

D

P 1000 mW 8.0 mW/°C 640 mW 520 mW

(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
(2) Tested in accordance with the Low-K thermal metric definitions of EIA/JESD51-3
(3) Tested in accordance with the High-K thermal metric definitions of EIA/JESD51-7

TA≤ 25°C DERATING FACTOR

POWER RATING ABOVE TA= 25°C POWER RATING POWER RATING

710 mW 5.7 mW/°C 455 mW 369 mW

1282 mW 10.3 mW/°C 821 mW 667 mW

(1)

TA= 70°C TA= 85°C

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

Supply voltage range, V
Voltage range at A or B -9 V to 14 V
Input voltage range at D, DE, R or RE -0.5 V to V
Voltage input range, transient pulse, A and B, through 100 Ω (see Figure 11 ) -50 V to 50 V
Receiver output current, I

Electrostatic discharge All pins 4 kV

Continuous total power dissipation See Dissipation Rating Table

(1) Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under" recommended operating

conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101.

2

CC

O

Human body model

Charged-device model

(3)

(4)

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(1) (2)

SN65HVD05, SN65HVD06, SN65HVD07
SN75HVD05, SN75HVD06, SN75HVD07

-0.3 V to 6 V

–11 mA to 11mA

A, B, and GND 16 kV

All pins 1 kV

+ 0.5 V

CC

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SN65HVD05 , , SN65HVD06
SN75HVD05 , SN65HVD07
SN75HVD06 , SN75HVD07

SLLS533D – MAY 2002 – REVISED JULY 2006

RECOMMENDED OPERATING CONDITIONS

MIN NOM MAX UNIT

Supply voltage, V
Voltage at any bus terminal (separately or common mode) VIor V
High-level input voltage, V
Low-level input voltage, V

CC

IC

IH

IL

D, DE, RE 2 V
D, DE, RE 0.8 V

Differential input voltage, VID(see Figure 7 ) -12 12 V

High-level output current, I

Low-level output current, I

OH

OL

Driver -100
Receiver -8
Driver 100
Receiver 8
SN65HVD05
SN65HVD06 -40 85 °C

Operating free-air temperature, T

SN65HVD07

A

SN75HVD05
SN75HVD06 0 70 °C
SN75HVD07

(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.

4.5 5.5 V

(1)

-7

12 V

mA

mA

DRIVER ELECTRICAL CHARACTERISTICS

over operating free-air temperature range unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP

V

IK

Input clamp voltage II= -18 mA -1.5 V

No Load V

|V

| Differential output voltage RL= 54 Ω , See Figure 4 2.5 V

OD

V

= -7 V to 12 V, See Figure 2 2.2

test

∆ |V

OD

V

OC(SS)

∆ V

OC(SS)

Change in magnitude of differential output

| See Figure 4 and Figure 2 -0.2 0.2 V

voltage
Steady-state common-mode output voltage 2.2 3.3 V
Change in steady-state common-mode

output voltage

See Figure 3

-0.1 0.1 V

HVD05 600

V

OC(PP)

Peak-to-peak common-mode
output voltage

HVD06 See Figure 3 500 mV
HVD07 900

I

OZ

I

I

I

OS

C

(diff)

High-impedance output current See receiver input currents

Input current µA

D -100 0

DE 0 100
Short-circuit output current -7 V ≤ VO≤ 12 V -250 250 mA
Differential output capacitance VID= 0.4 sin (4E6 π t) + 0.5 V, DE at 0 V 16 pF

RE at VCC,
D & DE at VCC, 9 15 mA
No load

Receiver disabled
and driver enabled

RE at VCC, Receiver disabled

I

CC

Supply current D at V

No load (standby)
RE at 0 V,

D & DE at VCC, 9 15 mA
No load

DE at 0 V, and driver disabled 1 5 µA

CC

Receiver enabled
and driver enabled

(1) All typical values are at 25°C and with a 5-V supply.

(1)

MAX UNIT

CC

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SN65HVD05 , , SN65HVD06
SN75HVD05 , SN65HVD07
SN75HVD06 , SN75HVD07

SLLS533D – MAY 2002 – REVISED JULY 2006

DRIVER SWITCHING CHARACTERISTICS

over operating free-air temperature range unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP

HVD05 6.5 11

t

PLH

t

PHL

t

r

t

f

t

sk(p)

t

sk(pp)

t

PZH1

t

PHZ

t

PZL1

t

PLZ

t

PZH2

t

PZL2

(1) All typical values are at 25°C and with a 5-V supply.
(2) t

Propagation delay time, low-to-high-level output HVD06 27 40 ns

HVD07 250 400
HVD05 6.5 11

Propagation delay time, high-to-low-level output HVD06 27 40 ns

HVD07 250 400
HVD05 2.7 3.6 6

Differential output signal rise time HVD06 18 28 55 ns

RL= 54 Ω , CL= 50 pF,
See Figure 4

HVD07 150 300 450
HVD05 2.7 3.6 6

Differential output signal fall time HVD06 18 28 55 ns

HVD07 150 300 450
HVD05 2

Pulse skew (|t

- t

PHL

|) HVD06 2.5 ns

PLH

HVD07 10
HVD05 3.5

(2)

Part-to-part skew HVD06 14 ns

HVD07 100

HVD05 25
Propagation delay time,
high-impedance-to-high-level output

Propagation delay time,
high-level-to-high-impedance output

HVD06 45 ns

HVD07 250

HVD05 25

RE at 0 V, RL= 110 Ω ,
See Figure 5

HVD06 60 ns

HVD07 250

HVD05 15
Propagation delay time,
high-impedance-to-low-level output

Propagation delay time,
low-level-to-high-impedance output

HVD06 45 ns

HVD07 200

HVD05 14

RE at 0 V, RL= 110 Ω ,
See Figure 6

HVD06 90 ns

HVD07 550
Propagation delay time, standby-to-high-level output 6 µs

Propagation delay time, standby-to-low-level output 6 µs

is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices

sk(pp)

operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.

RL= 110 Ω , RE at 3 V,
See Figure 5

RL= 110 Ω , RE at 3 V,
See Figure 6

(1)

MAX UNIT

4

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RECEIVER ELECTRICAL CHARACTERISTICS

over operating free-air temperature range unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP

Positive-going input

V

IT+

threshold voltage
Negative-going input

V

IT-

threshold voltage
Hysteresis voltage

V

hys

(V

- V

)

IT+

IT-

Enable-input clamp

V

IK

voltage

V

High-level output voltage VID= 200 mV, IOH= -8 mA, See Figure 7 4 V

OH

V

Low-level output voltage VID= -200 mV, IOL= 8 mA, See Figure 7 0.4 V

OL

High-impedance-state

I

OZ

output current

HVD05 Other inputat 0 V mA

I

Bus input current

I

HVD06
HVD07

High-level input current,

I

IH

RE
Low-level input current,

I

IL

RE
Differential input

C

(diff)

capacitance

I

Supply current D at VCC, No load (standby)

CC

(1) All typical values are at 25°C and with a 5-V supply.

IO= -8 mA 0.01

IO= 8 mA -0.2

II= -18 mA -1.5 V

VO= 0 or V

CC

Other inputat 0 V mA

VIH= 2 V -60 26.4 µA

VIL= 0.8 V -60 27.4 µA

VI= 0.4 sin (4E6 π t) + 0.5 V, DE at 0 V 16 pF
RE at 0 V, D & DE at

0 V, No load
RE at VCC, DE at 0 V, Receiver disabled and driver disabled

RE at 0 V,
D & DE at VCC, Receiver enabled and driver enabled 9 15 mA
No load

SN65HVD05 , , SN65HVD06
SN75HVD05 , SN65HVD07
SN75HVD06 , SN75HVD07

SLLS533D – MAY 2002 – REVISED JULY 2006

(1)

MAX UNIT

35 mV

RE at V

CC

VAor VB= 12 V 0.23 0.5
VAor VB= 12 V, V

= 0 V 0.3 0.5

CC

VAor VB= -7 V -0.4 0.13
VAor VB= -7 V, V

= 0 V -0.4 0.15

CC

VAor VB= 12 V 0.06 0.1
VAor VB= 12 V, V

= 0 V 0.08 0.13

CC

VAor VB= -7 V -0.1 0.05
VAor VB= -7 V, V

= 0 V -0.05 0.03

CC

Receiver enabled and driver disabled 5 10 mA

-1 1 µA

1 5 µA

V

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I

OA

V

OD 54 Ω ±1%

0 or 3 V

V

OA

V

OB

I

OB

DE

V

CC

I

I

V

I

A

B

60 Ω ±1%

V

OD

0 or 3 V

_

+ -7 V < V

(test)

< 12 V

DE

V

CC

A

B

D

375 Ω ±1%

375 Ω ±1%

SN65HVD05 , , SN65HVD06
SN75HVD05 , SN65HVD07
SN75HVD06 , SN75HVD07

SLLS533D – MAY 2002 – REVISED JULY 2006

RECEIVER SWITCHING CHARACTERISTICS

over operating free-air temperature range unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP

t

PLH

t

PHL

t

PLH

t

PHL

t

sk(p)

t

sk(pp)

t

r

t

f

t

PZH1

t

PZL1

t

PHZ

t

PLZ

t

PZH2

t

PZL2

Propagation delay time, low-to-high-level output 1/2 UL HVD05 14.6 25 ns
Propagation delay time, high-to-low-level output 1/2 UL HVD05 14.6 25 ns

Propagation delay time, low-to-high-level output 1/8 UL ns

Propagation delay time, high-to-low-level output 1/8 UL ns

Pulse skew (|t

(2)

Part-to-part skew HVD06 14 ns

- t

PHL

|) HVD06 4.5 ns

PLH

Output signal rise time 2 3
Output signal fall time 2 3
Output enable time to high level 10
Output enable time to low level 10
Output disable time from high level 15
Output disable time from low level 15
Propagation delay time, standby-to-high-level output 6
Propagation delay time, standby-to-low-level output 6

(1)

MAX UNIT

HVD06 55 70
HVD07 55 70

VID= -1.5 V to 1.5 V,

HVD06 CL= 15 pF, 55 70
HVD07 55 70

See Figure 8

HVD05 2

HVD07 4.5
HVD05 6.5

HVD07 14

CL= 15 pF,
See Figure 8

CL= 15 pF,
DE at 3 V, ns
See Figure 9

CL= 15 pF, DE at 0,
See Figure 10

ns

µs

(1) All typical values are at 25°C and with a 5-V supply.
(2) t

is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices

sk(pp)

operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.

Figure 1. Driver V

6

PARAMETER MEASUREMENT INFORMATION

Figure 2. Driver V

Test Circuit and Voltage and Current Definitions

OD

With Common-Mode Loading Test Circuit

OD

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V

OC

27 Ω ± 1%

Input

A

B

V

A

V

B

V

OC(PP)

∆V

OC(SS)

V

OC

27 Ω ± 1%

CL = 50 pF ±20%

D

A

B

DE

V

CC

Input: PRR = 500 kHz, 50% Duty Cycle,tr<6ns, tf<6ns, ZO = 50 Ω

CL Includes Fixture and
Instrumentation Capacitance

V

OD

RL = 54 Ω
± 1%

50 Ω

Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω

t

PLH

t

PHL

1.5 V 1.5 V

3 V

≈ 2 V

≈ –2 V

90%

10%

0 V

V

I

V

OD

t

r

t

f

CL = 50 pF ±20%
CL Includes Fixture

and Instrumentation
Capacitance

D

A

B

DE

V

CC

V

I

Input

Generator

90%

0 V

10%

0 V

RL = 110 Ω
± 1%

Input

Generator

50 Ω

Generator: PRR = 100 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω

3 V

S1

0.5 V

3 V

0 V

V

OH

≈ 0 V

t

PHZ

t

PZH(1 & 2)

1.5 V 1.5 V

V

I

V

O

CL = 50 pF ±20%

CL Includes Fixture

and Instrumentation

Capacitance

D

A

B

DE

V

O

V

I

2.3 V

Input

Generator

50 Ω

3 V

V

O

S1

1.5 V 1.5 V

t

PLZ

2.3 V

0.5 V

≈ 3 V

0 V

V

OL

V

I

V

O

Generator: PRR = 100 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω

RL = 110 Ω
± 1%

CL = 50 pF ±20%

CL Includes Fixture

and Instrumentation

Capacitance

D

A

B

DE

V

I

t

PZL(1 & 2)

V

CC

V

CC

SN65HVD05 , , SN65HVD06
SN75HVD05 , SN65HVD07
SN75HVD06 , SN75HVD07

SLLS533D – MAY 2002 – REVISED JULY 2006

PARAMETER MEASUREMENT INFORMATION (continued)

Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage

Figure 4. Driver Switching Test Circuit and Voltage Waveforms

Figure 5. Driver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms

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Figure 6. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms

7

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V

ID

V

A

V

B

I

O

A

B

I

B

V

O

R

I

A

V

IC

VA + V

B

2

Input

Generator

50 Ω

Generator: PRR = 100 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω

V

O

1.5 V

0 V

1.5 V 1.5 V

3 V

V

OH

V

OL

1.5 V
10%

1.5 V

t

PLH

t

PHL

t

r

t

f

90%

V

I

V

O

CL = 15 pF ±20%
CL Includes Fixture

and Instrumentation
Capacitance

A

B

RE

V

I

R

0 V

90%

10%

SN65HVD05 , , SN65HVD06
SN75HVD05 , SN65HVD07
SN75HVD06 , SN75HVD07

SLLS533D – MAY 2002 – REVISED JULY 2006

PARAMETER MEASUREMENT INFORMATION (continued)

Figure 7. Receiver Voltage and Current Definitions

Figure 8. Receiver Switching Test Circuit and Voltage Waveforms

8

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