SN55182, SN75182
DUAL DIFFERENTIAL LINE RECEIVERS
SLLS092D – OCTOBER 1972 – REVISED APRIL 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Single 5-V Supply
D
Differential Line Operation
D
Dual Channels
D
TTL Compatibility
D
±15-V Common-Mode Input Voltage Range
D
±15-V Differential Input Voltage Range
D
Individual Channel Strobes
D
Built-In Optional Line-Termination Resistor
D
Individual Frequency Response Controls
D
Designed for Use With Dual Differential
Drivers SN55183 and SN75183
D
Designed to Be Interchangeable With
National Semiconductor DS7820A and
DS8820A
description
The SN55182 and SN75182 dual differential line
receivers are designed to sense small differential
signals in the presence of large common-mode
noise. These devices give TTL-compatible output
signals as a function of the polarity of the
differential input voltage. The frequency response
of each channel can be easily controlled by a
single external capacitor to provide immunity to
differential noise spikes. The output goes to a high
level when the inputs are open circuited. A strobe
input (STRB) is provided that, when in the low
level, disables the receiver and forces the output
to a high level.
The receiver is of monolithic single-chip construction, and both halves of the dual circuits use common
power-supply and ground terminals.
The SN55182 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN75182 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUT
STRB V
ID
OUT
L X H
H HH
HLL
H = VI ≥ VIH min or VID more
positive than VTH max
L = VI ≤ V
IL
max or VID more
negative than VTL max
X = irrelevant
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1IN–
1R
T
1IN+
1STRB
1RTC
1OUT
GND
V
CC
2IN–
2R
T
2IN+
2STRB
2RTC
2OUT
SN55182 ...J OR W PACKAGE
SN75182 ...N PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
2R
T
NC
2IN+
NC
2STRB
1IN+
NC
1STRB
NC
1RTC
SN55182 . . . FK PACKAGE
(TOP VIEW)
1IN+
NC
2OUT
2RTC
2IN–
1OUT
GND
NC
CC
V
T
1R
NC – No internal connection
THE SN55182 IS NOT RECOMMENDED
FOR NEW DESIGNS
SN55182, SN75182
DUAL DIFFERENTIAL LINE RECEIVERS
SLLS092D – OCTOBER 1972 – REVISED APRIL 1998
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the J, N, and W packages.
&
3
1IN+
1
1IN–
RT
2
4
1STRB
RESP
5
1RTC
1OUT
6
11
2IN+
13
2IN–
12
10
2STRB
9
2RTC
2OUT
8
1R
T
2R
T
logic diagram (positive logic)
1OUT
3
1
2
5
4
1IN+
1IN–
1R
T
1RTC
1STRB
6
2OUT
11
13
12
9
10
2IN+
2IN–
2R
T
2RTC
2STRB
8
Pin numbers shown are for the J, N, and W packages.
SN55182, SN75182
DUAL DIFFERENTIAL LINE RECEIVERS
SLLS092D – OCTOBER 1972 – REVISED APRIL 1998
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematic (each receiver)
V
CC
OUT
GND
320 Ω
4.15 kΩ
1 kΩ
RTC
STRB
1.5 kΩ3 kΩ
750 Ω
1.5 kΩ
5 kΩ167 Ω
5 kΩ
1 kΩ
1 kΩ
167 Ω
167 Ω
5 kΩ170 Ω
5 kΩ
R
T
IN+
IN–
Resistor values shown are nominal.
Pin numbers shown are for the J, N, and W packages.
3, 11
2, 12
1, 13
14
6, 8
7
4, 10
5, 9
SN55182, SN75182
DUAL DIFFERENTIAL LINE RECEIVERS
SLLS092D – OCTOBER 1972 – REVISED APRIL 1998
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage, V
CC
(see Note 1) 8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Common-mode input voltage, V
IC
±20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, V
ID
(see Note 2) ±20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Strobe input voltage, V
I(STRB)
8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output sink current 50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package 260°C. . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J or W package 300°C. . . . . . . . . . . . . . . .
Case temperature for 60 seconds, T
c
: FK package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to network ground terminal.
2. Differential voltage values are at the noninverting terminal with respect to the inverting terminal.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 125°C
POWER RATING
FK
‡
1375 mW 11.0 mW/°C 880 mW 275 mW
J
‡
1375 mW 11.0 mW/°C 880 mW 275 mW
N 1150 mW 9.2 mW/°C 736 mW –
W
‡
1000 mW 8.0 mW/°C 640 mW 200 mW
‡
In the FK, J, and W packages, SN55182 chips are alloy mounted.
recommended operating conditions
SN55182 SN75182
MIN NOM MAX MIN NOM MAX
UNIT
Supply voltage, V
CC
4.5 5 5.5 4.5 5 5.5 V
Common-mode input voltage, V
IC
±15 ±15 V
High-level strobe input voltage, V
IH(STRB)
2.1 5.5 2.1 5.5 V
Low-level strobe input voltage, V
IL(STRB)
0 0.9 0 0.9 V
High-level output current, I
OH
–400 –400 µA
Low-level output current, I
OL
16 16 mA
Operating free-air temperature, T
A
–55 125 0 70 °C
SN55182, SN75182
DUAL DIFFERENTIAL LINE RECEIVERS
SLLS092D – OCTOBER 1972 – REVISED APRIL 1998
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of VCC, VIC, and operating free-air
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS
†
MIN TYP‡MAX UNIT
p
V
= 2.5 V,
VIC = –3 V to 3 V 0.5
V
IT+
Positive-going input threshold voltage
O
,
IOH = –400 µA
VIC = –15 V to 15 V 1
V
p
V
= 0.4 V,
VIC = –3 V to 3 V –0.5
V
IT–
Negative-going input threshold voltage
O
,
IOL = 16 mA
VIC = –15 V to 15 V –1
V
p
V
ID
= 1 V,
V
(STRB)
= 2.1 V,
I
OH
= –
400 µA
2.5
4.2
5.5
VOHHigh-level output voltage
V
V
ID
= –1 V,
V
(STRB)
= 0.4 V,
I
OH
= –
400 µA
2.5
4.2
5.5
p
VOLLow-level output voltage
V
ID
= –1 V,
V
(STRB)
= 2.1 V,
I
OL
= 16
mA
0.25
0.4
V
VIC = 15 V 3 4.2
Inverting input
VIC = 0 0 –0.5
p
VIC = –15 V –3 –4.2
IIInput current
VIC = 15 V 5 7
mA
Noninverting input
VIC = 0 –1 –1.4
VIC = –15 V –7 –9.8
I
IH(STRB)
High-level strobe input current V
(STRB)
= 5.5 V 5 µA
I
IL(STRB)
Low-level strobe input current V
(STRB)
= 0 –1 –1.4 mA
p
Inverting input 3.6 5
riInput resistance
Noninverting input 1.8 2.5
kΩ
Line-terminating resistance TA = 25°C 120 170 250 Ω
I
OS
Short-circuit output current VCC = 5.5 V, VO = 0 –2.8 –4.5 –6.7 mA
VIC = 15 V, VID = –1 V 4.2 6
I
CC
Supply current (average per receiver)
VIC = 0,
VID = –0.5 V 6.8 10.2
mA
VIC = –15 V, VID = –1 V 9.4 14
†
Unless otherwise noted, V
(STRB)
≥ 2.1 V or open.
‡
All typical values are at VCC = 5 V, VIC = 0, and TA = 25°C.
switching characteristics, VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PLH(D)
Propagation delay time,
low- to high-level output from differential input
RL = 400 Ω, CL = 15 pF, see Figure 1 18 40 ns
t
PHL(D)
Propagation delay time,
high- to low-level output from differential input
RL = 400 Ω, CL = 15 pF, see Figure 1 31 45 ns
t
PLH(S)
Propagation delay time,
low- to high-level output from STRB input
RL = 400 Ω, CL = 15 pF, see Figure 1 9 30 ns
t
PHL(S)
Propagation delay time,
high- to low-level output from STRB input
RL = 400 Ω, CL = 15 pF, see Figure 1 15 25 ns
SN55182, SN75182
DUAL DIFFERENTIAL LINE RECEIVERS
SLLS092D – OCTOBER 1972 – REVISED APRIL 1998
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WA VEFORMS
TEST CIRCUIT
CL = 15 pF
(see Note B)
See Note C
VCC = 5 V
400 Ω
50 Ω
Output
50 Ω
Strobe
Input
Input
t
PHL(D)
t
PLH(D)
Output
STRB
>100 ns
Input
>100 ns >100 ns>100 ns
t
PHL(S)
t
PLH(S)
V
OL
V
OH
0 V
2.6 V
–2.5 V
2.5 V
Pulse
Generator No. 2
(see Note A)
Pulse
Generator No. 1
(see Note A)
NOTES: A. The pulse generators have the following characteristics: ZO = 50 Ω, tr ≤ 10 ns, tf ≤ 10 ns, tw = 0.5 ±0.1 µs, PRR ≤ 1 MHz.
B. CL includes probe and jig capacitance.
C. All diodes are 1N3064 or equivalent.
t
w
t
w
1.3 V
0 V 0 V 0 V 0 V
1.3 V 1.3 V 1.3 V
1.3 V1.3 V 1.3 V 1.3 V
Figure 1. Test Circuit and Voltage Waveforms
SN55182, SN75182
DUAL DIFFERENTIAL LINE RECEIVERS
SLLS092D – OCTOBER 1972 – REVISED APRIL 1998
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
†
Figure 2
VID – Differential Input Threshold Voltage – V
DIFFERENTIAL INPUT THRESHOLD VOLTAGE
vs
SUPPLY VOLTAGE
0.2
0.1
0
–0.1
–0.2
5.55
–0.3
6
0.3
VCC – Supply Voltage – V
4.5
VO = 2.5 V, IO = –400 µA
VO = 0.4 V, IO = 16 mA
V
ID
VIC = 0
TA = 25°C
Figure 3
VIC – Common-Mode Input Voltage – V
VID – Differential Input Threshold Voltage – V
DIFFERENTIAL INPUT THRESHOLD VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
100–10
–0.5
20
0.5
–20
V
ID
VCC = 5 V
TA = 25°C
VO = 2.5 V, IO = –400 µA
VO = 0.4 V, IO = 16 mA
–15 –5 5 15
VID – Differential Input Threshold Voltage – V
DIFFERENTIAL INPUT THRESHOLD VOLTAGE
vs
FREE-AIR TEMPERATURE
50
0
–50
–100
–150
1007550250–25–50
–200
125
100
TA – Free-Air Temperature – °C
–75
V
ID
VCC = 5 V
VIC = 0
VO = 0.4 V, IO = 16 mA
VO = 2.5 V, IO = –400 µA
Figure 4
†
Operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
SN55182, SN75182
DUAL DIFFERENTIAL LINE RECEIVERS
SLLS092D – OCTOBER 1972 – REVISED APRIL 1998
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
†
Figure 5
VO – Output Voltage – V
OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
TA – Free-Air Temperature – °C
4
3
2
1
1007550250–25–50
0
125
5
–75
V
O
VCC = 5 V
VID = 0.5 V, IO = –400 µA
VID = –0.5 V , IOL = 16 mA
Figure 6
VO – Output Voltage – V
VOLTAGE TRANSFER CHARACTERISTICS
10 kΩ
VCC = 5 V
VIC = 0
5 V
4
3
2
1
0.30.1–0.1–0.3
0
0.5
5
VID – Differential Input Voltage – V
–0.5
V
O
TA = 125°C
TA = –55°C
–0.4 –0.2 0 0.2 0.4
TA = 25°C
400 Ω
4 Each
1N3064
From Output
Under Test
Figure 7
II – Input Current – mA
INPUT CURRENT
vs
INPUT VOLTAGE
8
6
4
2
0
–2
–4
–6
–8
100–10
–10
20
10
VI – Input Voltage – V
–20
I
I
IN–
–15 155–5
IN+
VCC = 5 V
VID = 0 to ±20 V
TA = 25°C
Figure 8
Terminating Resistance –
TERMINATING RESISTANCE
vs
FREE-AIR TEMPERATURE
180
170
160
1007550250–25–50
150
125
200
TA – Free-Air Temperature – °C
–75
Ω
190
†
Operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
SN55182, SN75182
DUAL DIFFERENTIAL LINE RECEIVERS
SLLS092D – OCTOBER 1972 – REVISED APRIL 1998
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
†
Figure 9
ICC – Supply Current – mA
SUPPLY CURRENT
(AVERAGE PER RECEIVER)
vs
COMMON-MODE INPUT VOLTAGE
10
8
6
4
2
0
12
VIC – Common-Mode Input Voltage – V
VID = –1 V
CC
I
VID = 1 V
100–10 20–20 –15 155–5
VCC = 5 V
No Load
TA = 25°C
Figure 10
PD – Power Dissipation – mW
POWER DISSIPATION
(AVERAGE PER RECEIVER)
vs
COMMON-MODE INPUT VOLTAGE
VIC – Common-Mode Input Voltage – V
200
100
0
300
P
D
TA = 25°C
TA = 125°C
100–10 20–20 –15 155–5
50
150
250
VCC = 5 V
VID = –1 V
Max Rated PD at TA = 125°C
(W Package )
†
Operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
SN55182, SN75182
DUAL DIFFERENTIAL LINE RECEIVERS
SLLS092D – OCTOBER 1972 – REVISED APRIL 1998
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
†
tw – Maximum Noise Pulse Duration – ns
t
w
0 V
– 2.5 V
2.5 V
MAXIMUM NOISE PULSE DURATION
vs
MAXIMUM RESPONSE TIME-CONTROL CAPACITANCE
4000100040010040
40
20
70
100
200
400
700
10
10000
1000
Response Time Control Capacitance – pF
10
INPUT PULSE
t
w
VCC = 5 V
TA = 25°C
See Note A
NOTE A: Figure 11 shows the maximum duration of the illustrated pulse that can be applied differently without the output changing from the
low to high level.
Figure 11
†
Operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
SN55182, SN75182
DUAL DIFFERENTIAL LINE RECEIVERS
SLLS092D – OCTOBER 1972 – REVISED APRIL 1998
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
†
Figure 12
PROPAGATION DELAY TIME
FROM DIFFERENTIAL INPUT
vs
FREE-AIR TEMPERATURE
34
30
26
22
18
1007550250–25–50
14
125
38
TA – Free-Air Temperature – °C
–75
VCC = 5 V
See Figure 1
t
PLH(D)
36
32
28
24
20
16
t
PHL(D)
– Propagation Delay Time From Differential Input – nst
P(D)
Figure 13
PROPAGATION DELAY TIME
FROM STROBE INPUT
vs
FREE-AIR TEMPERATURE
18
16
14
12
10
8
6
1007550250–25–50
4
125
20
TA – Free-Air Temperature – °C
–75
VCC = 5 V
See Figure 1
t
PHL(S)
– Propagation Delay Time From Strobe Input – nst
P(S)
t
PLH(S)
†
Operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
SN55182, SN75182
DUAL DIFFERENTIAL LINE RECEIVERS
SLLS092D – OCTOBER 1972 – REVISED APRIL 1998
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Twisted
Pair
RTC
OUT
100 pF
(see Note B)
STRB
0.002 µF
(see Note A)
1/2 ’182
VCC = 5 V
GND
Y
Z
GND
VCC = 5 V
1/2 ’183
Inputs
D
C
B
A
IN–
IN+
R
T
NOTES: A. When the inputs are open circuited, the output is high. A capacitor may be used for dc isolation of the line-terminating resistor.
At the frequency of operation, the impedance of the capacitor should be relatively small.
B. Use of a capacitor to control response time is optional.
Example: let f = 5 MHz
C = 0.002 µF
Z
(C)
[16W
Z
(C)
+
1
2pfC
+
1
2
p
ǒ
5 10
6
Ǔǒ
0.002 10
*
6
Ǔ
Figure 14. Transmission of Digital Data Over Twisted-Pair Line
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
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Copyright 1998, Texas Instruments Incorporated
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