TEXAS INSTRUMENTS SN54LVTH16244A, SN74LVTH16244A Technical data

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SN54LVTH16244A. . . WD PACKAGE

SN74LVTH16244A. . . DGG, DGV, OR DL PACKAGE

(TOP VIEW)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

1OE

1Y1
1Y2

GND

1Y3
1Y4
V

CC

2Y1
2Y2

GND

2Y3
2Y4
3Y1
3Y2

GND

3Y3
3Y4
V

CC

4Y1
4Y2

GND

4Y3
4Y4

4OE

2OE
1A1
1A2
GND
1A3
1A4
V

CC

2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
V

CC

4A1
4A2
GND
4A3
4A4
3OE

查询5962-9668501QXA供应商

FEATURES

• Members of the Texas Instruments

Widebus ™ Family

• State-of-the-Art Advanced BiCMOS

Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation

• Support Mixed-Mode Signal Operation

(5-V Input and Output Voltages With

3.3-V V

• Support Unregulated Battery Operation

Down to 2.7 V

• Typical V

<0.8 V at V

• I

and Power-Up 3-State Support Hot

off

Insertion

• Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

• Latch-Up Performance Exceeds 500 mA

Per JESD 17

• ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)

CC

)

OLP

CC

(Output Ground Bounce)

= 3.3 V, T

A

= 25 ° C

SN54LVTH16244A, SN74LVTH16244A

3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS

SCBS142Q – MAY 1992 – REVISED OCTOBER 2005

DESCRIPTION/ORDERING INFORMATION

The 'LVTH16244A devices are 16-bit buffers and line drivers designed for low-voltage (3.3-V) V
with the capability to provide a TTL interface to a 5-V system environment. These devices can be used as four
4-bit buffers, two 8-bit buffers, or one 16-bit buffer. These devices provide true outputs and symmetrical
active-low output-enable ( OE) inputs.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.

When V
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V
the minimum value of the resistor is determined by the current-sinking capability of the driver.

These devices are fully specified for hot-insertion applications using I
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.

Widebus is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.

CC

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

through a pullup resistor;

CC

and power-up 3-state. The I

off

Copyright © 1992–2005, Texas Instruments Incorporated

CC

operation, but

off

circuitry

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SN54LVTH16244A, SN74LVTH16244A

3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS

SCBS142Q – MAY 1992 – REVISED OCTOBER 2005

ORDERING INFORMATION

T

A

FBGA – GRD SN74LVTH16244AGRDR
FBGA – ZRD (Pb-free) SN74LVTH16244AZRDR

SSOP – DL SN74LVTH16244ADLR LVTH16244A

–40 ° C to 85 ° C

–55 ° C to 125 ° C CFP – WD Tube SNJ54LVTH16244AWD SNJ54LVTH16244AWD

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

TSSOP – DGG Tape and reel 74LVTH16244ADGGRE4 LVTH16244A

TVSOP – DGV Tape and reel LL244A

VFBGA – GQL SN74LVTH16244AGQLR
VFBGA – ZQL (Pb-free) SN74LVTH16244AZQLR

PACKAGE

(1)

Tape and reel LL244A

Tube SN74LVTH16244ADL

Tape and reel

Tape and reel LL244A

ORDERABLE PART NUMBER TOP-SIDE MARKING

74LVTH16244ADLRG4
SN74LVTH16244ADGGR

74LVTH16244ADGGRG4
SN74LVTH16244ADGVR
74LVTH16244ADGVRE4

2

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GQL OR ZQL PACKAGE

(TOP VIEW)

J

H

G

F

E

D

C

B

A

21 3 4 65

K

GRD OR ZRD PACKAGE

(TOP VIEW)

J

H

G

F

E

D

C

B

A

21 3 4 65

SN54LVTH16244A, SN74LVTH16244A

3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS

SCBS142Q – MAY 1992 – REVISED OCTOBER 2005

TERMINAL ASSIGNMENTS

(56-Ball GQL/ZQL Package)

1 2 3 4 5 6

A 1 OE NC NC NC NC 2 OE
B 1Y2 1Y1 GND GND 1A1 1A2
C 1Y4 1Y3 V
D 2Y2 2Y1 GND GND 2A1 2A2
E 2Y4 2Y3 2A3 2A4
F 3Y1 3Y2 3A2 3A1
G 3Y3 3Y4 GND GND 3A4 3A3
H 4Y1 4Y2 V

blk

blk

blk

J 4Y3 4Y4 GND GND 4A4 4A3

K 4 OE NC NC NC NC 3 OE

(1) NC – No internal connection

xxxxx
xxxxx
xxxxx

V

CC

V

CC

(1)

1A3 1A4

CC

4A2 4A1

CC

TERMINAL ASSIGNMENTS

(54-Ball GRD/ZRD Package)

1 2 3 4 5 6

A 1Y1 NC 1 OE 2 OE NC 1A1
B 1Y3 1Y2 NC NC 1A2 1A3
C 2Y1 1Y4 V
D 2Y3 2Y2 GND GND 2A2 2A3
E 3Y1 2Y4 GND GND 2A4 3A1
F 3Y3 3Y2 GND GND 3A2 3A3
G 4Y1 3Y4 V
H 4Y3 4Y2 NC NC 4A2 4A3

J 4Y4 NC 4 OE 3 OE NC 4A4

(1) NC – No internal connection

V

CC

CC

CC

V

CC

(1)

1A4 2A1

3A4 4A1

3

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1OE

1A1

1A2

1A3

1A4

1Y1

1Y2

1Y3

1Y4

1

47

46

44

43

2

3

5

6

2OE

2A1

2A2

2A3

2A4

2Y1

2Y2

2Y3

2Y4

48

41

40

38

37

8

9

11

12

3OE

3A1

3A2

3A3

3A4

3Y1

3Y2

3Y3

3Y4

25

36

35

33

32

13

14

16

17

4OE

4A1

4A2

4A3

4A4

4Y1

4Y2

4Y3

4Y4

24

30

29

27

26

19

20

22

23

Pin numbers shown are for the DGG, DGV , DL, and WD packages.

SN54LVTH16244A, SN74LVTH16244A

3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS

SCBS142Q – MAY 1992 – REVISED OCTOBER 2005

FUNCTION TABLE

(EACH 4-BIT BUFFER)

INPUTS

OE A

L H H
L L L

H X Z

LOGIC DIAGRAM (POSITIVE LOGIC)

OUTPUT

Y

4

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SN54LVTH16244A, SN74LVTH16244A

3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS

SCBS142Q – MAY 1992 – REVISED OCTOBER 2005

Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

V

Supply voltage range –0.5 4.6 V

CC

V

Input voltage range

I

V

Voltage range applied to any output in the high-impedance or power-off state

O

V

Voltage range applied to any output in the high state

O

I

Current into any output in the low state V

O

I

Current into any output in the high state

O

I

Input clamp current VI< 0 –50 mA

IK

I

Output clamp current VO< 0 –50 mA

OK

θ

Package thermal impedance

JA

T

Storage temperature range –65 150 ° C

stg

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) The current flows only when the output is in the high state and VO> VCC.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.

(2)

(1)

MIN MAX UNIT

–0.5 7 V

(2)

(2)

–0.5 7
–0.5 V

CC

SN54LVTH16244A 96
SN74LVTH16244A 128

(3)

SN54LVTH16244A 48
SN74LVTH16244A 64

DGG package 70
DGV package 58

(4)

DL package 63 ° C/W
GQL/ZQL package 42
GRD/ZRD package 36

+ 0.5

V

V

Recommended Operating Conditions

(1)

SN54LVTH16244A SN74LVTH16244A

MIN MAX MIN MAX

V

CC

V

IH

V

IL

V

I

I

OH

I

OL

Supply voltage 2.7 3.8 2.7 3.8 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input voltage 5.5 5.5 V
High-level output current –25 –32 mA
Low-level output current 48 64 mA

∆ t/ ∆ v Input transition rise or fall rate Outputs enabled 10 10 ns/V
∆ t/ ∆ V

T

A

(1) All unused inputs of the device must be held at V

Power-up ramp rate 200 200 µ s/V

CC

Operating free-air temperature –55 125 –40 85 ° C

or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

CC

UNIT

5

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SN54LVTH16244A, SN74LVTH16244A

3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS

SCBS142Q – MAY 1992 – REVISED OCTOBER 2005

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS UNIT

V

IK

V

OH

V

OL

V

= 2.7 V, II= –18 mA –1.2 –1.2 V

CC

V

= 2.7 V to 3.6 V, IOL= –100 µ A V

CC

V

= 2.7 V, IOH= –8 mA 2.4 2.4

CC

V

= 3 V

CC

V

= 2.7 V

CC

IOH= –24 mA 2
IOH= –32 mA 2
IOL= 100 µ A 0.2 0.2
IOL= 24 mA 0.5 0.5
IOL= 16 mA 0.4 0.4

V

= 3 V

CC

IOL= 32 mA 0.5 0.5
IOL= 48 mA 0.55
IOL= 64 mA 0.55

V

= 0 or 3.6 V, VI= 5.5 V 50 10

CC

Control
inputs

I

I

Data
inputs

I

off

Data VI= 2 V –75 –75

I

I(hold)

inputs

I

OZH

I

OZL

I

OZPU

I

OZPD

I

CC

(4)

∆ I

CC

C

i

C

o

(1) All typical values are at V
(2) This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to

V

= 3.6 V, VI= V

CC

V

= 3.6 V

CC

V

= 0, VIor V

CC

V

= 3 V

CC

V

CC

V

CC

V

CC

V

CC

OE = don't care
V

CC

OE = don't care
V

CC

IO= 0, Outputs low 5 5 mA
VI= V

V

CC

Other inputs at V

(2)

= 3.6 V

, VI= 0 to 3.6 V

= 3.6 V, VO= 3 V 5 5 µ A
= 3.6 V, VO= 0.5 V –5 –5 µ A
= 0 to 1.5 V, VO= 0.5 V to 3 V,

= 1.5 V to 0, VO= 0.5 V to 3 V,

= 3.6 V,

or GND

CC

= 3 V to 3.6 V, One input at V

VI= V
VI= 0 –5 –5

VI= 0.8 V 75 75

Outputs high 0.19 0.19

Outputs disabled 0.19 0.19

or GND

CC

or GND ± 1 ± 1

CC

CC

= 0 to 4.5 V ± 100 µ A

O

– 0.6 V,

CC

VI= 3 V or 0 V 4 4 pF
VO= 3 V or 0 V 9 9 pF

= 3.3 V, TA= 25 ° C.

CC

another.
(3) On products compliant to MIL-PRF-38535, this parameter does not apply.
(4) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V

SN54LVTH16244A SN74LVTH16244A

MIN TYP

– 0.2 V

CC

(1)

± 100

± 100

MAX MIN TYP

– 0.2

CC

(1)

MAX

1 1

– 750

(3)

(3)

± 100 µ A

± 100 µ A

0.2 0.2 mA

or GND.

CC

500

V

V

µ A

µ A

6

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SN54LVTH16244A, SN74LVTH16244A

3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS

SCBS142Q – MAY 1992 – REVISED OCTOBER 2005

Switching Characteristics

over recommended operating free-air temperature, CL= 50 pF (unless otherwise noted) (see Figure 1 )

SN54LVTH16244A SN74LVTH16244A

PARAMETER V

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

t

sk(o)

FROM TO V

(INPUT) (OUTPUT) ± 0.3 V ± 0.3 V

A Y ns

OE Y ns

OE Y ns

= 3.3 V V

CC

= 2.7 V V

CC

MIN MAX MIN MAX MIN TYP

= 3.3 V

CC

(1)

MAX MIN MAX

1.1 4.4 4.6 1.2 2.3 3.2 3.7

1.1 3.6 3.9 1.2 2 3.2 3.7

1.1 4.6 5.4 1.2 2.6 4 5

1.1 5.4 6.2 1.2 2.7 4 5

1.6 5.7 6.2 2.2 3.3 4.5 5

1.2 5 4.7 2 3.1 4.2 4.4

= 2.7 V UNIT

CC

0.5 ns

(1) All typical values are at V

= 3.3 V, TA= 25 ° C.

CC

7

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t

h

t

su

From Output

Under Test

C

L

= 50 pF

(see Note A)

LOAD CIRCUIT

S1

6 V

GND

500 Ω

500 Ω

Data Input

Timing Input

2.7 V

0 V

2.7 V

0 V

2.7 V

0 V

t

w

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

PULSE DURATION

t

PLH

t

PHL

t

PHL

t

PLH

V

OH

V

OH

V

OL

V

OL

2.7 V

0 V

Input

Output

Control

Output

Waveform 1

S1 at 6 V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

V

OL

V

OH

t

PZL

t

PZH

t

PLZ

t

PHZ

3 V

0 V

VOL + 0.3 V

VOH − 0.3 V

≈0 V

2.7 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Output

Output

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

Open

6 V

GND

TEST S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, t

f

≤ 2.5 ns.

D. The outputs are measured one at a time, with one transition per measurement.

Open

1.5 V 1.5 V

1.5 V 1.5 V

1.5 V 1.5 V

1.5 V 1.5 V

1.5 V

1.5 V 1.5 V

1.5 V 1.5 V

1.5 V

1.5 V

SN54LVTH16244A, SN74LVTH16244A

3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS

SCBS142Q – MAY 1992 – REVISED OCTOBER 2005

PARAMETER MEASUREMENT INFORMATION

8

Figure 1. Load Circuit and Voltage Waveforms

PACKAGE OPTION ADDENDUM

www.ti.com

4-Oct-2005

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package
Drawing

Pins Package

Qty

Eco Plan

5962-9668501QXA ACTIVE CFP WD 48 1 TBD Call TI Level-NC-NC-NC
5962-9668501VXA ACTIVE CFP WD 48 1 TBD Call TI Level-NC-NC-NC

74LVTH16244ADGGRE4 ACTIVE TSSOP DGG 48 2000 Green(RoHS &

no Sb/Br)

74LVTH16244ADGGRG4 ACTIVE TSSOP DGG 48 2000 Green (RoHS &

no Sb/Br)

74LVTH16244ADGVRE4 ACTIVE TVSOP DGV 48 2000 Green (RoHS &

no Sb/Br)

74LVTH16244ADLRG4 ACTIVE SSOP DL 48 1000 Green (RoHS &

no Sb/Br)

SN74LVTH16244ADGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS &

no Sb/Br)

SN74LVTH16244ADGVR ACTIVE TVSOP DGV 48 2000 Green (RoHS &

no Sb/Br)

SN74LVTH16244ADL ACTIVE SSOP DL 48 25 Green(RoHS &

no Sb/Br)

SN74LVTH16244ADLG4 ACTIVE SSOP DL 48 25 Green (RoHS &

no Sb/Br)

SN74LVTH16244ADLR ACTIVE SSOP DL 48 1000 Green (RoHS &

no Sb/Br)
SN74LVTH16244AGQLR ACTIVE VFBGA GQL 56 1000 TBD SNPB Level-1-240C-UNLIM
SN74LVTH16244AGRDR ACTIVE LFBGA GRD 54 1000 TBD SNPB Level-1-240C-UNLIM

SN74LVTH16244AZQLR ACTIVE VFBGA ZQL 56 1000 Green (RoHS &

no Sb/Br)
SN74LVTH16244AZRDR ACTIVE LFBGA ZRD 54 1000 Green (RoHS &

no Sb/Br)

SNJ54LVTH16244AWD ACTIVE CFP WD 48 1 TBD Call TI Level-NC-NC-NC

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

SNAGCU Level-1-260C-UNLIM

SNAGCU Level-1-260C-UNLIM

(3)

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

4-Oct-2005

Addendum-Page 2

MECHANICAL DATA

MCFP010B – JANUARY 1995 – REVISED NOVEMBER 1997

WD (R-GDFP-F**) CERAMIC DUAL FLATPACK

48 LEADS SHOWN

0.120 (3,05)

0.075 (1,91)

A

0.370 (9,40)

0.250 (6,35)

0.009 (0,23)

0.004 (0,10)

1.130 (28,70)

0.870 (22,10)

0.390 (9,91)

0.370 (9,40)

1

48

0.370 (9,40)

0.250 (6,35)

0.025 (0,635)

0.014 (0,36)

0.008 (0,20)

24

NO. OF

LEADS**

A MAX

A MIN

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only

E. Falls within MIL STD 1835: GDFP1-F48 and JEDEC MO-146AA

GDFP1-F56 and JEDEC MO-146AB

48

(16,26)

0.610

(15,49)

25

56

0.7400.640

(18,80)

0.710

(18,03)

4040176/D 10/97

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000

DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

0,40

24

112

A

0,23
0,13

13

0,07

4,50
4,30

M

6,60
6,20

0,16 NOM

Gage Plane

0,25

0°–8°

0,75
0,50

1,20 MAX

PINS **

DIM

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153

14/16/20/56 Pins – MO-194

0,15
0,05

14

3,70

3,50

Seating Plane

3,50

20

5,10

4,90

0,08

5,103,70

4,90

382416

7,90

7,70

48

9,80

9,60

56

11,40

11,20

4073251/E 08/00

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001

DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

48 PINS SHOWN

0.025 (0,635)

48

1

0.110 (2,79) MAX

0.0135 (0,343)

0.008 (0,203)
25

0.299 (7,59)

0.291 (7,39)

24

A

0.008 (0,20) MIN

0.005 (0,13)

0.420 (10,67)

0.395 (10,03)

Seating Plane

0.004 (0,10)

M

0.010 (0,25)

0.005 (0,13)

Gage Plane

0.010 (0,25)

0°–ā8°

0.040 (1,02)

0.020 (0,51)

PINS **

DIM

A MAX

A MIN

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118

0.380

(9,65)

0.370

(9,40)

4828

0.630

(16,00)

0.620

(15,75)

56

0.730

(18,54)

0.720

(18,29)

4040048/E 12/01

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MTSS003D – JANUARY 1995 – REVISED JANUARY 1998

DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

48 PINS SHOWN

0,50

48

1

1,20 MAX

0,27
0,17

25

24

A

0,15
0,05

0,08

M

6,20

8,30

6,00

7,90

Seating Plane

0,10

0,15 NOM

Gage Plane

0,25

0°–8°

0,75
0,50

DIM

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

PINS **

A MAX

A MIN

48

12,60

12,40

56

14,10

13,90

64

17,10

16,90

4040078/F 12/97

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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