TEXAS INSTRUMENTS SN54LVTH16244A, SN74LVTH16244A Technical data

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SN54LVTH16244A. . . WD PACKAGE

SN74LVTH16244A. . . DGG, DGV, OR DL PACKAGE

(TOP VIEW)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

1OE

1Y1 1Y2

GND

1Y3 1Y4 V

CC

2Y1 2Y2

GND

2Y3 2Y4 3Y1 3Y2

GND

3Y3 3Y4 V

CC

4Y1 4Y2

GND

4Y3 4Y4

4OE

2OE 1A1 1A2 GND 1A3 1A4 V

CC

2A1 2A2 GND 2A3 2A4 3A1 3A2 GND 3A3 3A4 V

CC

4A1 4A2 GND 4A3 4A4 3OE

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FEATURES

• Members of the Texas Instruments

Widebus ™ Family

• State-of-the-Art Advanced BiCMOS

Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation

• Support Mixed-Mode Signal Operation

(5-V Input and Output Voltages With

3.3-V V

• Support Unregulated Battery Operation

Down to 2.7 V

• Typical V

<0.8 V at V

• I

and Power-Up 3-State Support Hot

off

Insertion

• Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

• Latch-Up Performance Exceeds 500 mA

Per JESD 17

• ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A)

CC

)

OLP

CC

(Output Ground Bounce)

= 3.3 V, T

A

= 25 ° C

SN54LVTH16244A, SN74LVTH16244A

3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

SCBS142Q – MAY 1992 – REVISED OCTOBER 2005

DESCRIPTION/ORDERING INFORMATION

The 'LVTH16244A devices are 16-bit buffers and line drivers designed for low-voltage (3.3-V) V with the capability to provide a TTL interface to a 5-V system environment. These devices can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. These devices provide true outputs and symmetrical active-low output-enable ( OE) inputs.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

When V However, to ensure the high-impedance state above 1.5 V, OE should be tied to V the minimum value of the resistor is determined by the current-sinking capability of the driver.

These devices are fully specified for hot-insertion applications using I disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

Widebus is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.

CC

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

through a pullup resistor;

CC

and power-up 3-state. The I

off

CC

operation, but

off

circuitry

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SN54LVTH16244A, SN74LVTH16244A

3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

SCBS142Q – MAY 1992 – REVISED OCTOBER 2005

ORDERING INFORMATION

T

A

FBGA – GRD SN74LVTH16244AGRDR FBGA – ZRD (Pb-free) SN74LVTH16244AZRDR

SSOP – DL SN74LVTH16244ADLR LVTH16244A

–40 ° C to 85 ° C

–55 ° C to 125 ° C CFP – WD Tube SNJ54LVTH16244AWD SNJ54LVTH16244AWD

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

TSSOP – DGG Tape and reel 74LVTH16244ADGGRE4 LVTH16244A

TVSOP – DGV Tape and reel LL244A

VFBGA – GQL SN74LVTH16244AGQLR VFBGA – ZQL (Pb-free) SN74LVTH16244AZQLR

PACKAGE

(1)

Tape and reel LL244A

Tube SN74LVTH16244ADL

Tape and reel

Tape and reel LL244A

ORDERABLE PART NUMBER TOP-SIDE MARKING

74LVTH16244ADLRG4 SN74LVTH16244ADGGR

74LVTH16244ADGGRG4 SN74LVTH16244ADGVR 74LVTH16244ADGVRE4

2

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GQL OR ZQL PACKAGE

(TOP VIEW)

J

H

G

F

E

D

C

B

A

21 3 4 65

K

GRD OR ZRD PACKAGE

(TOP VIEW)

J

H

G

F

E

D

C

B

A

21 3 4 65

SN54LVTH16244A, SN74LVTH16244A

3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

SCBS142Q – MAY 1992 – REVISED OCTOBER 2005

TERMINAL ASSIGNMENTS

(56-Ball GQL/ZQL Package)

1 2 3 4 5 6

A 1 OE NC NC NC NC 2 OE B 1Y2 1Y1 GND GND 1A1 1A2 C 1Y4 1Y3 V D 2Y2 2Y1 GND GND 2A1 2A2 E 2Y4 2Y3 2A3 2A4 F 3Y1 3Y2 3A2 3A1 G 3Y3 3Y4 GND GND 3A4 3A3 H 4Y1 4Y2 V

blk

J 4Y3 4Y4 GND GND 4A4 4A3

K 4 OE NC NC NC NC 3 OE

(1) NC – No internal connection

xxxxx xxxxx xxxxx

V

CC

V

CC

(1)

1A3 1A4

CC

4A2 4A1

CC

TERMINAL ASSIGNMENTS

(54-Ball GRD/ZRD Package)

1 2 3 4 5 6

A 1Y1 NC 1 OE 2 OE NC 1A1 B 1Y3 1Y2 NC NC 1A2 1A3 C 2Y1 1Y4 V D 2Y3 2Y2 GND GND 2A2 2A3 E 3Y1 2Y4 GND GND 2A4 3A1 F 3Y3 3Y2 GND GND 3A2 3A3 G 4Y1 3Y4 V H 4Y3 4Y2 NC NC 4A2 4A3

J 4Y4 NC 4 OE 3 OE NC 4A4

(1) NC – No internal connection

V

CC

V

CC

(1)

1A4 2A1

3A4 4A1

3

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1OE

1A1

1A2

1A3

1A4

1Y1

1Y2

1Y3

1Y4

1

47

46

44

43

2

3

5

6

2OE

2A1

2A2

2A3

2A4

2Y1

2Y2

2Y3

2Y4

48

41

40

38

37

8

9

11

12

3OE

3A1

3A2

3A3

3A4

3Y1

3Y2

3Y3

3Y4

25

36

35

33

32

13

14

16

17

4OE

4A1

4A2

4A3

4A4

4Y1

4Y2

4Y3

4Y4

24

30

29

27

26

19

20

22

23

Pin numbers shown are for the DGG, DGV , DL, and WD packages.

SN54LVTH16244A, SN74LVTH16244A

3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

SCBS142Q – MAY 1992 – REVISED OCTOBER 2005

FUNCTION TABLE

(EACH 4-BIT BUFFER)

INPUTS

OE A

L H H L L L

H X Z

LOGIC DIAGRAM (POSITIVE LOGIC)

OUTPUT

Y

4

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SN54LVTH16244A, SN74LVTH16244A

3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

SCBS142Q – MAY 1992 – REVISED OCTOBER 2005

Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

V

Supply voltage range –0.5 4.6 V

CC

V

Input voltage range

I

V

Voltage range applied to any output in the high-impedance or power-off state

O

V

Voltage range applied to any output in the high state

O

I

Current into any output in the low state V

O

I

Current into any output in the high state

O

I

Input clamp current VI< 0 –50 mA

IK

I

Output clamp current VO< 0 –50 mA

OK

θ

Package thermal impedance

JA

T

Storage temperature range –65 150 ° C

stg

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. (3) The current flows only when the output is in the high state and VO> VCC. (4) The package thermal impedance is calculated in accordance with JESD 51-7.

(2)

(1)

MIN MAX UNIT

–0.5 7 V

(2)

–0.5 7 –0.5 V

CC

SN54LVTH16244A 96 SN74LVTH16244A 128

(3)

SN54LVTH16244A 48 SN74LVTH16244A 64

DGG package 70 DGV package 58

(4)

DL package 63 ° C/W GQL/ZQL package 42 GRD/ZRD package 36

+ 0.5

V

Recommended Operating Conditions

(1)

SN54LVTH16244A SN74LVTH16244A

MIN MAX MIN MAX

V

CC

V

IH

V

IL

V

I

OH

I

OL

Supply voltage 2.7 3.8 2.7 3.8 V High-level input voltage 2 2 V Low-level input voltage 0.8 0.8 V Input voltage 5.5 5.5 V High-level output current –25 –32 mA Low-level output current 48 64 mA

∆ t/ ∆ v Input transition rise or fall rate Outputs enabled 10 10 ns/V ∆ t/ ∆ V

T

A

(1) All unused inputs of the device must be held at V

Power-up ramp rate 200 200 µ s/V

CC

Operating free-air temperature –55 125 –40 85 ° C

or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

CC

UNIT

5

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SN54LVTH16244A, SN74LVTH16244A

3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

SCBS142Q – MAY 1992 – REVISED OCTOBER 2005

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS UNIT

V

IK

V

OH

V

OL

V

= 2.7 V, II= –18 mA –1.2 –1.2 V

CC

V

= 2.7 V to 3.6 V, IOL= –100 µ A V

CC

V

= 2.7 V, IOH= –8 mA 2.4 2.4

CC

V

= 3 V

CC

V

= 2.7 V

CC

IOH= –24 mA 2 IOH= –32 mA 2 IOL= 100 µ A 0.2 0.2 IOL= 24 mA 0.5 0.5 IOL= 16 mA 0.4 0.4

V

= 3 V

CC

IOL= 32 mA 0.5 0.5 IOL= 48 mA 0.55 IOL= 64 mA 0.55

V

= 0 or 3.6 V, VI= 5.5 V 50 10

CC

Control inputs

I

Data inputs

I

off

Data VI= 2 V –75 –75

I

I(hold)

inputs

I

OZH

I

OZL

I

OZPU

I

OZPD

I

CC

(4)

∆ I

CC

C

i

C

o

(1) All typical values are at V (2) This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to

V

= 3.6 V, VI= V

CC

V

= 3.6 V

CC

V

= 0, VIor V

CC

V

= 3 V

CC

V

CC

V

CC

V

CC

V

CC

OE = don't care V

CC

OE = don't care V

CC

IO= 0, Outputs low 5 5 mA VI= V

V

CC

Other inputs at V

(2)

= 3.6 V

, VI= 0 to 3.6 V

= 3.6 V, VO= 3 V 5 5 µ A = 3.6 V, VO= 0.5 V –5 –5 µ A = 0 to 1.5 V, VO= 0.5 V to 3 V,

= 1.5 V to 0, VO= 0.5 V to 3 V,

= 3.6 V,

or GND

CC

= 3 V to 3.6 V, One input at V

VI= V VI= 0 –5 –5

VI= 0.8 V 75 75

Outputs high 0.19 0.19

Outputs disabled 0.19 0.19

or GND

CC

or GND ± 1 ± 1

CC

= 0 to 4.5 V ± 100 µ A

O

– 0.6 V,

CC

VI= 3 V or 0 V 4 4 pF VO= 3 V or 0 V 9 9 pF

= 3.3 V, TA= 25 ° C.

CC

another. (3) On products compliant to MIL-PRF-38535, this parameter does not apply. (4) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V

SN54LVTH16244A SN74LVTH16244A

MIN TYP

– 0.2 V

CC

(1)

± 100

MAX MIN TYP

– 0.2

CC

(1)

MAX

1 1

– 750

(3)

± 100 µ A

0.2 0.2 mA

or GND.

CC

500

V

µ A

6