TEXAS INSTRUMENTS SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373 Technical data
...
SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002
D
Choice of Eight Latches or Eight D-Type
Flip-Flops in a Single Package
D
3-State Bus-Driving Outputs
D
Full Parallel Access for Loading
D
Buffered Control Inputs
D
Clock-Enable Input Has Hysteresis to
Improve Noise Rejection (’S373 and ’S374)
D
P-N-P Inputs Reduce DC Loading on Data
Lines (’S373 and ’S374)
description
These 8-bit registers feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. The
high-impedance 3-state and increased
high-logic-level drive provide these registers with
the capability of being connected directly to and
driving the bus lines in a bus-organized system
without need for interface or pullup components.
These devices are particularly attractive for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
The eight latches of the ’LS373 and ’S373 are
transparent D-type latches, meaning that while
the enable (C or CLK) input is high, the Q outputs
follow the data (D) inputs. When C or CLK is taken
low, the output is latched at the level of the data
that was set up.
The eight flip-flops of the ’LS374 and ’S374 are
edge-triggered D-type flip-flops. On the positive
transition of the clock, the Q outputs are set to the
logic states that were set up at the D inputs.
SN54LS373, SN54LS374, SN54S373,
SN74LS373, SN74S374 . . . DW, N, OR NS PACKAGE
SN54S374 . . . J OR W PACKAGE
SN74LS374 . . . DB, DW, N, OR NS PACKAGE
SN74S373 . . . DW OR N PACKAGE
†
C for ’LS373 and ’S373; CLK for ’LS374 and ’S374.
SN54LS373, SN54LS374, SN54S373,
SN54S374 . . . FK PACKAGE
2D
2Q
3Q
3D
4D
†
C for ’LS373 and ’S373; CLK for ’LS374 and ’S374.
(TOP VIEW)
1
OC
2
1Q
3
1D
4
2D
5
2Q
6
3Q
7
3D
8
4D
9
4Q
GND
10
(TOP VIEW)
1D1QOC
3212019
4
5
6
7
8
910111213
4Q
†
GND
20
V
CC
19
8Q
18
8D
17
7D
16
7Q
15
6Q
14
6D
13
5D
12
5Q
†
11
C
CC
8Q
V
8D
18
7D
17
7Q
16
6Q
15
6D
14
5D
C
5Q
Schmitt-trigger buffered inputs at the enable/clock lines of the ’S373 and ’S374 devices simplify system design
as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered
output-control (OC
) input can be used to place the eight outputs in either a normal logic state (high or low logic
levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly.
OC
does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new
data can be entered, even while the outputs are off.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1
SN54LS373, SN54LS374, SN54S373, SN54S374,
PDIP
N
LS373
LS374
0°C to 70°C
SOIC
DW
S373
S374
CDIP
J
LCCC
FK
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002
ORDERING INFORMATION
T
A
°
°
SOP – NS
SSOP – DB Tape and reel SN74LS374DBR LS374A
–55°C to 125°C
CFP – W
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
PACKAGE
–
–
–
–
†
Tube SN74LS373N SN74LS373N
Tube SN74LS374N SN74LS374N
Tube SN74S373N SN74S373N
Tube SN74S374N SN74S374N
Tube SN74LS373DW
Tape and reel SN74LS373DWR
Tube SN74LS374DW
Tape and reel SN74LS374DWR
Tube SN74S373DW
Tape and reel SN74S373DWR
Tube SN74S374DW
Tape and reel SN74S374DWR
Tape and reel SN74LS373NSR 74LS373
Tape and reel SN74LS374NSR 74LS374
Tape and reel SN74S374NSR 74S374
Tube SN54LS373J SN54LS373J
Tube SNJ54LS373J SNJ54LS373J
Tube SN54LS374J SN54LS374J
Tube SNJ54LS374J SNJ54LS374J
Tube SN54S373J SN54S373J
Tube SNJ54S373J SNJ54S373J
Tube SN54S374J SN54S374J
Tube SNJ54S374J SNJ54S374J
Tube SNJ54LS373W SNJ54LS373W
Tube SNJ54LS374W SNJ54LS374W
Tube SNJ54S374W SNJ54S374W
Tube SNJ54LS373FK SNJ54LS373FK
Tube SNJ54LS374FK SNJ54LS374FK
Tube SNJ54S373FK SNJ54S373FK
Tube SNJ54S374FK SNJ54S374FK
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002
Function Tables
’LS373, ’S373
(each latch)
INPUTS
OC C D
L H H H
L HL L
L LX Q
H X X Z
’LS374, ’S374
(each latch)
INPUTS
OC CLK D
L ↑ H H
L ↑ LL
L LX Q
H X X Z
OUTPUT
Q
0
OUTPUT
Q
0
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002
logic diagrams (positive logic)
OC
1D
2D
3D
4D
5D
’LS373, ’S373
Transparent Latches
1
11
C
3
4
7
8
13
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
12
2
1Q
5
2Q
6
3Q
9
4Q
5Q
OC
CLK
1D
2D
3D
4D
5D
Positive-Edge-Triggered Flip-Flops
1
11
3
4
7
8
13
’LS374, ’S374
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
12
2
1Q
5
2Q
6
3Q
9
4Q
5Q
14
6D
17
7D
18
8D
Pin numbers shown are for DB, DW, J, N, NS, and W packages.
C1
1D
C1
1D
C1
1D
for ’S373 Only
15
16
19
6Q
7Q
8Q
6D
7D
8D
14
17
18
C1
1D
C1
1D
C1
1D
for ’S374 Only
15
16
19
6Q
7Q
8Q
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
schematic of inputs and outputs
’LS373
EQUIVALENT OF DATA INPUTS EQUIVALENT OF ENABLE- AND
V
CC
Req = 20 kΩ NOM
Input
OUTPUT-CONTROL INPUTS
V
CC
Input
17 kΩ NOM
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002
TYPICAL OF ALL OUTPUTS
V
CC
100 Ω NOM
Output
EQUIVALENT OF DATA INPUTS
V
CC
30 kΩ NOM
Input
’LS374
EQUIVALENT OF CLOCK- AND
OUTPUT-CONTROL INPUTS
V
CC
17 kΩ NOM
Input
TYPICAL OF ALL OUTPUTS
100 Ω NOM
V
CC
Output
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54LS373, SN54LS374, SN54S373, SN54S374,
UNIT
twPulse duration
ns
tsuData setup time
ns
thData hold time
ns
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
(’LS devices)
Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
Off-state output voltage 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 2): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. V oltage values are with respect to network ground terminal.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions
SN54LS’ SN74LS’
MIN NOM MAX MIN NOM MAX
V
V
I
OH
I
OL
T
‡
The th specification applies only for data frequency below 10 MHz. Designs above 10 MHz should use a minimum of 5 ns (commercial only).
Supply voltage 4.5 5 5 4.75 5 5.25 V
CC
High-level output voltage 5.5 5.5 V
OH
High-level output current –1 –2.6 mA
Low-level output current 12 24 mA
CLK high 15 15
CLK low 15 15
p
Operating free-air temperature –55 125 0 70 °C
A
’LS373 5↓ 5↓
’LS374 20↑ 20↑
’LS373 20↓ 20↓
‡
’LS374
5↑ 0↑
†
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER
TEST CONDITIONS
†
UNIT
VOHHigh-level output voltage
CC
,
IH
,
2.4
3.4
2.4
3.1
V
VOLLow-level output voltage
CC
,
IH
,
V
I
,
CC
,
IH
,
20
20mA
I
,
CC
,
IH
,
20–20mA
I
V
MAX
V
7 V
0.1
0.1
mA
ICCSupply current
CC
,
mA
PARAMETER
TEST CONDITIONS
UNIT
Data
Any Q
L
,
L
,
ns
C or CLK
Any Q
L
,
L
,
ns
OC
Any Q
L
,
L
,
ns
t
152515
28
OC
Any Q
R
667 Ω
C
5 pF
ns
t
122012
20
SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LS’ SN74LS’
MIN TYP‡MAX MIN TYP‡MAX
V
High-level input voltage 2 2 V
IH
V
Low-level input voltage 0.7 0.8 V
IL
V
Input clamp voltage VCC = MIN, II = –18 mA –1.5 –1.5 V
IK
V
p
p
Off-state output current, V
OZH
high-level voltage applied
Off-state output current, V
OZL
low-level voltage applied
Input current at maximum
I
input voltage
I
High-level input current VCC = MAX, VI = 2.7 V 20 20
IH
I
Low-level input current VCC = MAX, VI = 0.4 V –0.4 –0.4 mA
IL
I
Short-circuit output current§VCC = MAX –30 –130 –30 –130 mA
OS
pp
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡
All typical values are at VCC = 5 V, TA = 25°C.
§
Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.
= MIN, V
VIL = VIL max,
V
= MIN, V
VIL = VIL max
= MAX, V
VO = 2.7 V
= MAX, V
VO = 0.4 V
,
=
CC
V
= MAX,
Output control at 4.5 V
= 2 V,
IOH = MAX
= 2 V,
= 2 V,
= 2 V,
=
I
IOL = 12 mA 0.25 0.4 0.25 0.4
IOL = 24 mA 0.35 0.5
–
’LS373 24 40 24 40
’LS374 27 40 27 40
m
A
switching characteristics, V
FROM TO
(INPUT) (OUTPUT)
f
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
PHZ
PLZ
NOTE 3: Maximum clock frequency is tested with all outputs loaded.
f
= maximum clock frequency
max
t
= propagation delay time, low-to-high-level output
PLH
t
= propagation delay time, high-to-low-level output
PHL
t
= output enable time to high level
PZH
t
= output enable time to low level
PZL
t
= output disable time from high level
PHZ
t
= output disable time from low level
PLZ
= 5 V, TA = 25°C (see Figure 1)
CC
RL = 667 Ω, CL = 45 pF,
See Note 3
R
= 667 Ω, C
See Note 3
R
= 667 Ω, C
See Note 3
R
= 667 Ω, C
See Note 3
,
=
L
= 45 pF,
= 45 pF,
= 45 pF,
p
=
L
’LS373 ’LS374
MIN TYP MAX MIN TYP MAX
35 50 MHz
12 18
12 18
20 30 15 28
18 30 19 28
15 28 20 26
25 36 21 28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002
schematic of inputs and outputs
’S373 and ’S374 ’S373 and ’S374
EQUIVALENT OF EACH INPUT
V
CC
2.8 kΩ NOM
Input
TYPICAL OF ALL OUTPUTS
50 Ω NOM
V
CC
Output
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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