SOIC
DW
LS245
CDIP
J
55°C to 125°C
SN54LS245, SN74LS245
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SDLS146A – OCTOBER 1976 – REVISED FEBRUARY 2002
D
3-State Outputs Drive Bus Lines Directly
D
PNP Inputs Reduce dc Loading on Bus
Lines
D
Hysteresis at Bus Inputs Improves Noise
Margins
D
Typical Propagation Delay Times Port to
Port, 8 ns
I
OL
TYPE
SN54LS245 12 mA –12 mA
SN74LS245 24 mA –15 mA
(SINK
CURRENT)
I
OH
(SOURCE
CURRENT)
description
These octal bus transceivers are designed for
asynchronous two-way communication between
data buses. The control-function implementation
minimizes external timing requirements.
The devices allow data transmission from the
A bus to the B bus or from the B bus to the A bus,
depending on the logic level at the
direction-control (DIR) input. The output-enable
(OE
) input can disable the device so that the
buses are effectively isolated.
SN54LS245 ...J OR W PACKAGE
SN74LS245 ... DB, DW, N, OR NS PACKAGE
SN54LS245 . . . FK P ACKAGE
A3
A4
A5
A6
A7
(TOP VIEW)
1
DIR
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
A8
GND
10
(TOP VIEW)
A2A1DIR
3 2 1 20 19
4
5
6
7
8
910111213
A8
B8
20
19
18
17
16
15
14
13
12
11
V
B7
CC
V
OE
B1
B2
B3
B4
B5
B6
B7
B8
OE
18
17
16
15
14
B6
CC
B1
B2
B3
B4
B5
GND
T
A
PDIP – N Tube SN74LS245N SN74LS245N
0°C to 70°C
SOP – NS Tape and reel SN74LS245NSR 74LS245
SSOP – DB T ape and reel SN74LS245DBR LS245
°
–
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
°
CFP – W Tube SNJ54LS245W SNJ54LS245W
LCCC – FK Tube SN54LS245FK SN54LS245FK
ORDERING INFORMA TION
PACKAGE
–
–
†
Tube SN74LS245DW
Tape and reel SN74LS245DWR
Tube SN54LS245J SN54LS245J
Tube SNJ54LS245J SNJ54LS245J
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54LS245, SN74LS245
OPERATION
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SDLS146A – OCTOBER 1976 – REVISED FEBRUARY 2002
schematics of inputs and outputs
FUNCTION TABLE
INPUTS
OE DIR
L L B data to A bus
L H A data to B bus
H X Isolation
EQUIVALENT OF EACH INPUT
V
CC
9 kΩ NOM
Input
logic diagram (positive logic)
DIR
TYPICAL OF ALL OUTPUTS
V
CC
50 Ω NOM
Output
1
19
OE
2
2
A1
To Seven Other Channels
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
18
B1
UNIT
SN54LS245, SN74LS245
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SDLS146A – OCTOBER 1976 – REVISED FEBRUARY 2002
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
Input voltage, V
Package thermal impedance,
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
q
(see Note 2): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions
SN54LS245 SN74LS245
MIN NOM MAX MIN NOM MAX
V
I
I
T
OH
OL
Supply voltage 4.5 5 5.5 4.75 5 5.25 V
CC
High-level output current –12 –15 mA
Low-level output current 12 24 mA
Operating free-air temperature –55 125 0 70 °C
A
†
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54LS245, SN74LS245
PARAMETER
TEST CONDITIONS
†
UNIT
VOHHigh-level output voltage
V
2 V
V
VOLLow-level output voltage
V
2 V
V
I
t
V
MAX
mA
C
45 pF
R
667 W
t
Propagation delay time, high- to low-level output
8
12
C
45 pF
R
667 W
ns
C
5 pF
R
667 W
ns
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SDLS146A – OCTOBER 1976 – REVISED FEBRUARY 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LS245 SN74LS245
MIN TYP‡MAX MIN TYP‡MAX
V
High-level input voltage 2 2 V
IH
V
Low-level input voltage 0.7 0.8 V
IL
V
Input clamp voltage VCC = MIN, II = –18 mA –1.5 –1.5 V
IK
Hysteresis (VT+ – VT–) A or B VCC = MIN 0.2 0.4 0.2 0.4 V
p
p
Off-state output current,
I
OZH
high-level voltage applied
Off-state output current,
I
OZL
low-level voltage applied
Input current at
maximum inpu
I
voltage
I
High-level input current VCC = MAX, VIH = 2.7 V 20 20 µA
IH
I
Low-level input current VCC = MAX, VIL = 0.4 V –0.2 –0.2 mA
IL
I
Short-circuit output current
OS
I
Supply current
CC
†
For conditions shown as MIN or MAX, use the appropriate values specified under recommended operating conditions.
‡
All typical values are at VCC = 5 V, TA = 25°C.
§
Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second.
A or B
p
DIR or OE
§
Total, outputs high 48 70 48 70
Total, outputs low
Outputs at high Z 64 95 64 95
VCC = MIN,
VIL = V
VCC = MIN,
VIL = V
VCC = MAX,
OE
VCC = MAX,
OE
VCC = MAX –40 –225 40 –225 mA
VCC = MAX Outputs open
=
IH
=
IH
at 2 V
at 2 V
CC
,
IL(max)
,
IL(max)
=
IOH = –3 mA 2.4 3.4 2.4 3.4
IOH = MAX 2 2
IOL = 12 mA 0.4 0.4
IOL = 24 mA 0.5
VO = 2.7 V 20 20 µA
VO = 0.4 V –200 –200 µA
VI = 5.5 V 0.1 0.1
VI = 7 V 0.1 0.1
62 90 62 90
mA
switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1)
PARAMETER TEST CONDITIONS MIN TYP MAX
t
PLH
PHL
t
PZL
t
PZH
t
PLZ
t
PHZ
Propagation delay time, low- to high-level output
p
Output enable time to low level
Output enable time to high level
Output disable time from low level
Output disable time from high level
p
,
=
L
p
,
=
L
p
,
=
L
UNIT
=
L
=
L
=
L
8 12
27 40
25 40
15 25
15 28
ns
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
(see Note A)
Test
Point
C
L
SDLS146A – OCTOBER 1976 – REVISED FEBRUARY 2002
PARAMETER MEASUREMENT INFORMATION
SERIES 54LS/74LS DEVICES
V
CC
V
CC
R
L
R
(see Note B)
From Output
Under Test
(see Note A)
C
L
L
Test
Point
SN54LS245, SN74LS245
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
V
CC
From Output
Under Test
(see Note A)
Test
R
Point
C
L
L
S1
(see Note B)
5 kΩ
S2
FOR 2-STATE TOTEM-POLE OUTPUTS
High-Level
Low-Level
In-Phase
(see Note D)
Out-of-Phase
(see Note D)
NOTES: A. CL includes probe and jig capacitance.
LOAD CIRCUIT
Pulse
Pulse
Input
t
PLH
Output
t
PHL
Output
PROPAGATION DELAY TIMES
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. S1 and S2 are closed for t
E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.
F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns, tf ≤ 2.6 ns.
G. The outputs are measured one at a time with one input transition per measurement.
1.3 V 1.3 V
t
w
1.3 V 1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.3 V 1.3 V
1.3 V 1.3 V
1.3 V 1.3 V
VOLTAGE WAVEFORMS
, t
PLH
PHL
t
PHL
t
PLH
, t
FOR OPEN-COLLECTOR OUTPUTS
PHZ
LOAD CIRCUIT
3 V
0 V
V
OH
V
OL
V
OH
V
OL
, and t
PLZ
Timing
Input
Data
Input
Output
Control
(low-level
enabling)
t
PZL
Waveform 1
(see Notes C
and D)
t
PZH
Waveform 2
(see Notes C
and D)
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
; S1 is open and S2 is closed for t
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
1.3 V
t
su
1.3 V 1.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.3 V 1.3 V
1.3 V
1.3 V
VOLTAGE WAVEFORMS
; S1 is closed and S2 is open for t
PZH
3 V
0 V
t
h
3 V
0 V
3 V
0 V
t
PLZ
≈1.5 V
VOL + 0.5 V
V
OL
t
PHZ
V
OH
VOH – 0.5 V
≈1.5 V
.
PZL
Figure 1. Load Circuits and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jun-2005
PACKAGING INFORMATION
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
5962-8002101VRA ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NC
5962-8002101VSA ACTIVE CFP W 20 1 TBD Call TI Level-NC-NC-NC
80021012A ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NC
8002101SA ACTIVE CFP W 20 1 TBD Call TI Level-NC-NC-NC
JM38510/32803B2A ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NC
JM38510/32803BRA ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NC
JM38510/32803BSA ACTIVE CFP W 20 1 TBD Call TI Level-NC-NC-NC
SN54LS245J ACTIVE CDIP J 20 1 TBD CallTI Level-NC-NC-NC
SN74LS245DBR ACTIVE SSOP DB 20 2000 Pb-Free
SN74LS245DBRE4 ACTIVE SSOP DB 20 2000 Pb-Free
SN74LS245DW ACTIVE SOIC DW 20 25 Pb-Free
SN74LS245DWG4 ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br)
SN74LS245DWR ACTIVE SOIC DW 20 2000 Pb-Free
SN74LS245DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br)
SN74LS245J OBSOLETE CDIP J 20 TBD Call TI Call TI
SN74LS245N ACTIVE PDIP N 20 20 Pb-Free
SN74LS245N3 OBSOLETE PDIP N 20 TBD Call TI Call TI
SN74LS245NSR ACTIVE SO NS 20 2000 Pb-Free
SN74LS245NSRE4 ACTIVE SO NS 20 2000 Pb-Free
SN74LS245NSRG4 ACTIVE SO NS 20 2000 Green (RoHS &
no Sb/Br)
SNJ54LS245FK ACTIVE LCCC FK 20 1 TBD CallTI Level-NC-NC-NC
SNJ54LS245J ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NC
SNJ54LS245W ACTIVE CFP W 20 1 TBD Call TI Level-NC-NC-NC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(RoHS)
(RoHS)
(RoHS)
(RoHS)
(RoHS)
(RoHS)
(RoHS)
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-NC-NC-NC
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
(3)
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
8-Jun-2005
Addendum-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A SQ
B SQ
20
22
23
24
25
19
21
12826 27
12
1314151618 17
0.020 (0,51)
0.010 (0,25)
MIN
0.342
(8,69)
0.442
0.640
0.739
0.938
1.141
A
0.358
(9,09)
0.458
(11,63)
0.660
(16,76)
0.761
(19,32)(18,78)
0.962
(24,43)
1.165
(29,59)
NO. OF
TERMINALS
**
11
10
9
8
7
6
5
432
20
28
44
52
68
84
0.020 (0,51)
0.010 (0,25)
(11,23)
(16,26)
(23,83)
(28,99)
MINMAX
0.307
(7,80)
0.406
(10,31)
0.495
(12,58)
0.495
(12,58)
0.850
(21,6)
1.047
(26,6)
0.080 (2,03)
0.064 (1,63)
B
MAX
0.358
(9,09)
0.458
(11,63)
0.560
(14,22)
0.560
(14,22)
0.858
(21,8)
1.063
(27,0)
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
4040140/D 10/96
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,65
28
1
2,00 MAX
0,38
0,22
15
14
A
0,05 MIN
0,15
5,60
5,00
M
8,20
7,40
Seating Plane
0,10
0,25
0,09
0°–ā8°
Gage Plane
0,25
0,95
0,55
PINS **
DIM
A MAX
A MIN
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
14
6,50
6,50
5,905,90
2016
7,50
6,90
24
8,50
28
10,50
9,907,90
30
10,50
9,90
38
12,90
12,30
4040065 /E 12/01
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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