Texas Instruments JM38510-65760BRA, SN54HCT540J, SN74HCT540DW, SN74HCT540DWR, SN74HCT540N Datasheet
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SN54HCT540, SN74HCT540
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS008B – MARCH 1984 – REVISED MA Y 1997
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Inputs Are TTL-Voltage Compatible
D
High-Current 3-State Outputs Interface
Directly With System Bus or Can Drive up
to 15 LSTTL Loads
D
Data Flow-Through Pinout (All Inputs on
Opposite Side From Outputs)
D
Package Options Include Plastic
Small-Outline (DW) and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs
description
These octal buffers and line drivers are designed
to have the performance of the ’HCT240 and a
pinout with inputs and outputs on opposite sides
of the package. This arrangement greatly
facilitates printed circuit board layout.
The 3-state control gate is a 2-input NOR. If either
output-enable (OE1
or OE2) input is high, all eight
outputs are in the high-impedance state. The
’HCT540 provide inverted data at the outputs.
The SN54HCT540 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74HCT540 is characterized for
operation from –40°C to 85°C.
FUNCTION TABLE
(each buffer/driver)
INPUTS
OUTPUT
OE1 OE2
A
Y
L L L H
L LH L
H XX Z
X H X Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE1
A1
A2
A3
A4
A5
A6
A7
A8
GND
V
CC
OE2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
SN54HCT540 ...J OR W PACKAGE
SN74HCT540 . . . DW OR N PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
Y1
Y2
Y3
Y4
Y5
A3
A4
A5
A6
A7
A2A1OE1
Y7
Y6
V
OE2
A8
GND
Y8
SN54HCT540 . . . FK PACKAGE
(TOP VIEW)
CC
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN54HCT540, SN74HCT540
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS008B – MARCH 1984 – REVISED MA Y 1997
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
2
A1
3
A2
4
A3
1
Y1
18
Y2
17
Y3
16
&
EN
5
A4
6
A5
7
A6
Y4
15
Y5
14
Y6
13
19
OE1
OE2
8
A7
9
A8
Y7
12
Y8
11
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
OE1
OE2
To Seven Other Channels
A1
Y1
1
19
218
absolute maximum ratings over operating free-air temperature range
‡
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±35 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND ±70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2): DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
SN54HCT540, SN74HCT540
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS008B – MARCH 1984 – REVISED MA Y 1997
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
SN54HCT540 SN74HCT540
MIN NOM MAX MIN NOM MAX
UNIT
V
CC
Supply voltage 4.5 5 5.5 4.5 5 5.5 V
V
IH
High-level input voltage VCC = 4.5 V to 5.5 V 2 2 V
V
IL
Low-level input voltage VCC = 4.5 V to 5.5 V 0 0.8 0 0.8 V
V
I
Input voltage 0 V
CC
0 V
CC
V
V
O
Output voltage 0 V
CC
0 V
CC
V
t
t
Input transition (rise and fall) time 0 500 0 500 ns
T
A
Operating free-air temperature –55 125 –40 85 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54HCT540 SN74HCT540
PARAMETER
TEST CONDITIONS
V
CC
MIN TYP MAX MIN MAX MIN MAX
UNIT
IOH = –20 µA
4.4 4.499 4.4 4.4
V
OH
V
I
=
V
IH
or V
IL
IOH = –6 mA
4.5 V
3.98 4.3 3.7 3.84
V
IOL = 20 µA
0.001 0.1 0.1 0.1
V
OL
V
I
=
V
IH
or
V
IL
IOL = 6 mA
4.5 V
0.17 0.26 0.4 0.33
V
I
I
VI = VCC or 0 5.5 V ±0.1 ±100 ±1000 ±1000 nA
I
OZ
VO = VCC or 0, VI = VIH or V
IL
5.5 V ±0.01 ±0.5 ±10 ±5 µA
I
CC
VI = VCC or 0, IO = 0 5.5 V 8 160 80 µA
∆I
CC
†
One input at 0.5 V or 2.4 V ,
Other inputs at 0 or V
CC
5.5 V 1.4 2.4 3 2.9 mA
C
i
4.5 V
to 5.5 V
3 10 10 10 pF
†
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
FROM TO
TA = 25°C SN54HCT540 SN74HCT540
PARAMETER
(INPUT) (OUTPUT)
V
CC
MIN TYP MAX MIN MAX MIN MAX
UNIT
4.5 V 13 20 30 25
tpdA
Y
5.5 V 12 18 27 23
ns
4.5 V 20 30 45 38
t
en
OE
Y
5.5 V 18 27 41 34
ns
4.5 V 19 30 45 38
t
dis
OE
Y
5.5 V 18 27 41 34
ns
4.5 V 8 12 18 15
ttY
5.5 V 7 11 16 14
ns
SN54HCT540, SN74HCT540
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS008B – MARCH 1984 – REVISED MA Y 1997
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, CL = 150 pF
(unless otherwise noted) (see Figure 1)
FROM TO
TA = 25°C SN54HCT540 SN74HCT540
PARAMETER
(INPUT) (OUTPUT)
V
CC
MIN TYP MAX MIN MAX MIN MAX
UNIT
4.5 V 20 30 45 38
tpdA
Y
5.5 V 19 27 41 34
ns
4.5 V 26 40 60 50
t
en
OE
Y
5.5 V 25 36 54 45
ns
4.5 V 17 42 63 53
ttY
5.5 V 14 38 57 48
ns
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
pd
Power dissipation capacitance per buffer/driver No load 35 pF
SN54HCT540, SN74HCT540
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS008B – MARCH 1984 – REVISED MA Y 1997
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
R
L
V
CC
S1
S2
LOAD CIRCUIT
PARAMETER C
L
t
PZH
tpd or t
t
t
dis
t
en
t
PZL
t
PHZ
t
PLZ
1 kΩ
1 kΩ
50 pF
or
150 pF
50 pF
Open Closed
R
L
S1
Closed Open
S2
Open Closed
Closed Open
50 pF
or
150 pF
Open Open––
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as ten.
G. t
PLH
and t
PHL
are the same as tpd.
C
L
(see Note A)
Test
Point
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
1.3 V1.3 V
0.3 V0.3 V
2.7 V 2.7 V
3 V
0 V
t
r
t
f
Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
1.3 V
1.3 V1.3 V
10%10%
90% 90%
3 V
V
OH
V
OL
0 V
t
r
t
f
Input
In-Phase
Output
1.3 V
t
PLH
t
PHL
1.3 V 1.3 V
10% 10%
90%90%
V
OH
V
OL
t
r
t
f
t
PHL
t
PLH
Out-of-
Phase
Output
1.3 V
10%
90%
3 V
≈ V
CC
V
OL
0 V
Output
Control
(Low-Level
Enabling)
Output
Waveform 1
(See Note B)
1.3 V
t
PZL
t
PLZ
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
V
OH
≈ 0 V
1.3 V
1.3 V
t
PZH
t
PHZ
Output
Waveform 2
(See Note B)
Figure 1. Load Circuit and Voltage Waveforms
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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Copyright 1998, Texas Instruments Incorporated
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