Texas Instruments SN54HCT373J, SN74HCT373DW, SN74HCT373DWR, SN74HCT373N, SN74HCT373N3 Datasheet
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SN54HCT373, SN74HCT373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS009B – MARCH 1984 – REVISED MA Y 1997
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Inputs Are TTL-Voltage Compatible
D
Eight High-Current Latches in a Single
Package
D
High-Current 3-State True Outputs Can
Drive up to 15 LSTTL Loads
D
Full Parallel Access for Loading
D
Package Options Include Plastic
Small-Outline (DW) and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs
description
These 8-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight latches of the ’HCT373 are transparent
D-type latches. While the latch-enable (LE) input
is high, the Q outputs follow the data (D) inputs.
When LE is taken low, the Q outputs are latched
at the levels that were set up at the D inputs.
An output-enable (OE
) input places the eight
outputs in either a normal logic state (high or low
logic levels) or the high-impedance state. In the
high-impedance state, the outputs neither load
nor drive the bus lines significantly. The
high-impedance state and increased drive
provide the capability to drive bus lines without
interface or pullup components.
OE
does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are off.
The SN54HCT373 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74HCT373 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
3212019
910111213
4
5
6
7
8
18
17
16
15
14
8D
7D
7Q
6Q
6D
2D
2Q
3Q
3D
4D
1D1QOE
5Q
5D
V
8Q
4Q
GND
LE
SN54HCT373 . . . FK PACKAGE
(TOP VIEW)
CC
SN54HCT373 ...J OR W PACKAGE
SN74HCT373 . . . DW OR N PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN54HCT373, SN74HCT373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS009B – MARCH 1984 – REVISED MA Y 1997
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
OE LE D
Q
L H H H
L HL L
L LX Q
0
H X X Z
logic symbol
†
1D
3
1D
4
2D
7
3D
EN
1
1Q
2
2Q
5
3Q
6
8
4D
13
5D
14
6D
4Q
9
5Q
12
6Q
15
OE
17
7D
18
8D
C1
11
LE
7Q
16
8Q
19
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
OE
To Seven Other Channels
1
11
3
2
LE
1D
C1
1D
1Q
SN54HCT373, SN74HCT373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS009B – MARCH 1984 – REVISED MA Y 1997
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range
†
Supply voltage range, V
CC
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±35 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2): DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
recommended operating conditions
SN54HCT373 SN74HCT373
MIN NOM MAX MIN NOM MAX
UNIT
V
CC
Supply voltage 4.5 5 5.5 4.5 5 5.5 V
V
IH
High-level input voltage VCC = 4.5 V to 5.5 V 2 2 V
V
IL
Low-level input voltage VCC = 4.5 V to 5.5 V 0 0.8 0 0.8 V
V
I
Input voltage 0 V
CC
0 V
CC
V
V
O
Output voltage 0 V
CC
0 V
CC
V
t
t
Input transition (rise and fall) time 0 500 0 500 ns
T
A
Operating free-air temperature –55 125 –40 85 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54HCT373 SN74HCT373
PARAMETER
TEST CONDITIONS
V
CC
MIN TYP MAX MIN MAX MIN MAX
UNIT
IOH = –20 µA
4.4 4.499 4.4 4.4
V
OH
V
I
=
V
IH
or
V
IL
IOH = –6 mA
4.5 V
3.98 4.3 3.7 3.84
V
IOL = 20 µA
0.001 0.1 0.1 0.1
V
OL
V
I
=
V
IH
or
V
IL
IOL = 6 mA
4.5 V
0.17 0.26 0.4 0.33
V
I
I
VI = VCC or 0 5.5 V ±0.1 ±100 ±1000 ±1000 nA
I
OZ
VO = VCC or 0 5.5 V ±0.01 ±0.5 ±10 ±5 µA
I
CC
VI = VCC or 0, IO = 0 5.5 V 8 160 80 µA
∆I
CC
‡
One input at 0.5 V or 2.4 V ,
Other inputs at 0 or V
CC
5.5 V 1.4 2.4 3 2.9 mA
C
i
4.5 V
to 5.5 V
3 10 10 10 pF
‡
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
SN54HCT373, SN74HCT373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS009B – MARCH 1984 – REVISED MA Y 1997
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
TA = 25°C SN54HCT373 SN74HCT373
V
CC
MIN MAX MIN MAX MIN MAX
UNIT
4.5 V 20 30 25
twPulse duration, LE high
5.5 V 17 27 23
ns
p
4.5 V 10 15 13
tsuSetup time, data before LE↓
5.5 V 9 14 12
ns
4.5 V 10 10 10
thHold time, data after LE↓
5.5 V 10 10 10
ns
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
FROM TO
TA = 25°C SN54HCT373 SN74HCT373
PARAMETER
(INPUT) (OUTPUT)
V
CC
MIN TYP MAX MIN MAX MIN MAX
UNIT
4.5 V 25 35 53 44
D
Q
5.5 V 21 32 48 40
t
pd
4.5 V 28 35 53 44
ns
LE
Any Q
5.5 V 25 32 48 40
4.5 V 26 35 53 44
t
en
OE
Any Q
5.5 V 23 32 48 40
ns
4.5 V 23 35 53 44
t
dis
OE
Any Q
5.5 V 22 32 48 40
ns
4.5 V 10 12 18 15
ttAny Q
5.5 V 9 11 16 14
ns
switching characteristics over recommended operating free-air temperature range, CL = 150 pF
(unless otherwise noted) (see Figure 1)
FROM TO
TA = 25°C SN54HCT373 SN74HCT373
PARAMETER
(INPUT) (OUTPUT)
V
CC
MIN TYP MAX MIN MAX MIN MAX
UNIT
4.5 V 32 52 79 65
D
Q
5.5 V 27 47 71 59
t
pd
4.5 V 38 52 79 65
ns
LE
Any Q
5.5 V 36 47 71 59
4.5 V 33 52 79 65
t
en
OE
Any Q
5.5 V 28 47 71 59
ns
4.5 V 18 42 63 53
ttAny Q
5.5 V 16 38 57 48
ns
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
pd
Power dissipation capacitance per latch No load 50 pF
SN54HCT373, SN74HCT373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS009B – MARCH 1984 – REVISED MA Y 1997
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
t
h
t
su
1.3 V
1.3 V1.3 V
0.3 V0.3 V
2.7 V 2.7 V
3 V
3 V
0 V
0 V
t
r
t
f
Reference
Input
Data
Input
1.3 V
High-Level
Pulse
1.3 V
3 V
0 V
1.3 V
1.3 V
3 V
0 V
t
w
Low-Level
Pulse
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
1.3 V
1.3 V1.3 V
10%10%
90% 90%
3 V
V
OH
V
OL
0 V
t
r
t
f
Input
In-Phase
Output
1.3 V
t
PLH
t
PHL
1.3 V 1.3 V
10% 10%
90%90%
V
OH
V
OL
t
r
t
f
t
PHL
t
PLH
Out-of-
Phase
Output
1.3 V
10%
90%
3 V
≈ V
CC
V
OL
0 V
Output
Control
(Low-Level
Enabling)
Output
Waveform 1
(See Note B)
1.3 V
t
PZL
t
PLZ
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
V
OH
≈ 0 V
1.3 V
1.3 V
t
PZH
t
PHZ
Output
Waveform 2
(See Note B)
Test
Point
From Output
Under Test
R
L
V
CC
S1
S2
LOAD CIRCUIT
PARAMETER C
L
t
PZH
tpd or t
t
t
dis
t
en
t
PZL
t
PHZ
t
PLZ
1 kΩ
1 kΩ
50 pF
or
150 pF
50 pF
Open Closed
R
L
S1
Closed Open
S2
Open Closed
Closed Open
50 pF
or
150 pF
Open Open––
C
L
(see Note A)
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as ten.
G. t
PLH
and t
PHL
are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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Copyright 1998, Texas Instruments Incorporated
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