TEXAS INSTRUMENTS SN54HCT32, SN74HCT32 Technical data

SOIC – D
HCT32
–40°C to 85°C
TSSOP – PW
HT32
–55°C to 125°C
SN54HCT32, SN74HCT32
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SCLS064E – NOVEMBER 1988 – REVISED AUGUST 2003
D
Operating Voltage Range of 4.5 V to 5.5 V
D
D
Low Power Consumption, 20-µA Max I
SN54HCT32 ...J OR W PACKAGE
SN74HCT32 . . . D, DB, N, NS, OR PW PACKAGE
1A 1B 1Y 2A 2B 2Y
GND
(TOP VIEW)
1
14
2
13
3
12
4
11
5
10 6 7
V
CC
4B 4A 4Y 3B
9
3A
8
3Y
CC
D
Typical t
D
±4-mA Output Drive at 5 V
D
Low Input Current of 1 µA Max
D
Inputs Are TTL-Voltage Compatible
= 13 ns
pd
SN54HCT32 . . . FK PACKAGE
1Y
NC
2A
NC
2B
NC – No internal connection
(TOP VIEW)
1B1ANC
3212019
4 5 6 7 8
910111213
2Y
GND
NC
V
3Y
CC
4B
18 17 16 15 14
3A
4A NC 4Y NC 3B
description/ordering information
The ’HCT32 devices contain four independent 2-input OR gates. They perform the Boolean function
Y+A
B or Y+A)B
in positive logic.
ORDERING INFORMA TION
T
A
PDIP – N Tube of 25 SN74HCT32N SN74HCT32N
SOP – NS Reel of 2000 SN74HCT32NSR HCT32 SSOP – DB Reel of 2000 SN74HCT32DBR HT32
CDIP – J Tube of 25 SNJ54HCT32J SNJ54HCT32J CFP – W T ube of 150 SNJ54HCT32W SNJ54HCT32W LCCC – FK Tube of 55 SNJ54HCT32FK SNJ54HCT32FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
PACKAGE
Tube of 50 SN74HCT32D Reel of 2500 SN74HCT32DR Reel of 250 SN74HCT32DT
Tube of 90 SN74HCT32PW Reel of 2000 SN74HCT32PWR Reel of 250 SN74HCT32PWT
ORDERABLE
PART NUMBER
TOP-SIDE MARKING
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
1
SN54HCT32, SN74HCT32
OUTPUT
OUTPUT
UNIT
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SCLS064E – NOVEMBER 1988 – REVISED AUGUST 2003
FUNCTION TABLE
INPUTS
A B
H X H X HH
L L L
logic diagram (positive logic)
(each gate)
Y
A B
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V Input clamp current, I Output clamp current, I Continuous output current, I Continuous current through V Package thermal impedance, θ
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
(VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 2): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
Y
DB package 96°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 76°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 3)
SN54HCT32 SN74HCT32
MIN NOM MAX MIN NOM MAX
V V V V V t/v Input transition rise/fall time 500 500 ns T
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 4.5 5 5.5 4.5 5 5.5 V
CC
High-level input voltage VCC = 4.5 V to 5.5 V 2 2 V
IH
Low-level input voltage VCC = 4.5 V to 5.5 V 0.8 0.8 V
IL
Input voltage 0 V
I
Output voltage 0 V
O
Operating free-air temperature –55 125 –40 85 °C
A
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
CC CC
0 V 0 V
CC CC
V V
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER
TEST CONDITIONS
V
CC
UNIT
V
OH
VI = VIH or V
IL
4.5 V
V
V
OL
VI = VIH or V
IL
4.5 V
V
FROM
TO
PARAMETER
FROM
TO
V
CC
UNIT
tpdA or B
Y
ns
ttY
ns
SN54HCT32, SN74HCT32
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SCLS064E – NOVEMBER 1988 – REVISED AUGUST 2003
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C SN54HCT32 SN74HCT32
MIN TYP MAX MIN MAX MIN MAX
IOH = –20 µA IOH = –4 mA IOL = 20 µA IOL = 4 mA
I
I
I
CC
I
CC
C
i
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
VI = VCC or 0 5.5 V ±0.1 ±100 ±1000 ±1000 nA VI = VCC or 0, IO = 0 5.5 V 2 40 20 µA One input at 0.5 V or 2.4 V,
Other inputs at 0 or V
CC
5.5 V 1.4 2.4 3 2.9 mA
4.5 V
to 5.5 V
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
(INPUT)
(OUTPUT)
4.5 V 15 24 35 30
5.5 V 13 22 32 27
4.5 V 9 15 22 19
5.5 V 8 14 20 17
4.4 4.499 4.4 4.4
3.98 4.3 3.7 3.84
0.001 0.1 0.1 0.1
0.17 0.26 0.4 0.33
3 10 10 10 pF
TA = 25°C SN54HCT32 SN74HCT32
MIN TYP MAX MIN MAX MIN MAX
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
Power dissipation capacitance per gate No load 20 pF
pd
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3
SN54HCT32, SN74HCT32
3 V
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SCLS064E – NOVEMBER 1988 – REVISED AUGUST 2003
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
LOAD CIRCUIT
Input
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
C. The outputs are measured one at a time with one input transition per measurement. D. t
2.7 V 2.7 V
t
r
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
characteristics: PRR 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
and t
PLH
PHL
Test Point
CL = 50 pF (see Note A)
are the same as tpd.
3 V
1.3 V1.3 V
0.3 V0.3 V
0 V
t
f
Figure 1. Load Circuit and Voltage Waveforms
Input
In-Phase
Output
Out-of-Phase
Output
PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
1.3 V
t
PLH
90% 90%
t
PHL
1.3 V 1.3 V 10% 10%
VOLTAGE WAVEFORMS
1.3 V 0 V
t
PHL
V
1.3 V1.3 V
t
r
t
PLH
t
f
OH
10%10%
V
OL
t
f
V
OH
90%90%
V
OL
t
r
4
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