SN54HCT08, SN74HCT08
SOIC – D
HCT08
–40°C to 85°C
TSSOP – PW
HT08
–55°C to 125°C
f
QUADRUPLE 2-INPUT POSITIVE-AND GATES
SCLS063D – NOVEMBER 1988 – REVISED AUIGUST 2003
D
Operating Voltage Range of 4.5 V to 5.5 V
D
Outputs Can Drive Up To 10 LSTTL Loads
D
Low Power Consumption, 20-µA Max I
SN54HCT08 ...J OR W PACKAGE
SN74HCT08 . . . D, DB, N, NS, OR PW PACKAGE
1A
1B
1Y
2A
2B
2Y
GND
(TOP VIEW)
1
14
2
13
3
12
4
11
5
10
6
7
V
CC
4B
4A
4Y
3B
9
3A
8
3Y
CC
D
Typical t
D
±4-mA Output Drive at 5 V
D
Low Input Current of 1 µA Max
D
Inputs Are TTL-Voltage Compatible
= 13 ns
pd
SN54HCT08 . . . FK PACKAGE
1Y
NC
2A
NC
2B
NC – No internal connection
(TOP VIEW)
1B1ANC
3212019
4
5
6
7
8
910111213
2Y
NC
GND
CC
V
3Y
4B
18
17
16
15
14
3A
4A
NC
4Y
NC
3B
description/ordering information
These devices contain four independent 2-input AND gates. They perform the Boolean function
)
Y+A • BorY+A
B
in positive logic.
ORDERING INFORMA TION
T
A
PDIP – N Tube of 25 SN74HCT08N SN74HCT08N
SOP – NS Reel of 2000 SN74HCT08NSR HCT08
SSOP – DB Reel of 2000 SN74HCT08DBR HT08
CDIP – J Tube of 25 SNJ54HCT08J SNJ54HCT08J
CFP – W T ube of 150 SNJ54HCT08W SNJ54HCT08W
LCCC – FK Tube of 55 SNJ54HCT08FK SNJ54HCT08FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
PACKAGE
†
Tube of 50 SN74HCT08D
Reel of 2500 SN74HCT08DR
Reel of 250 SN74HCT08DT
Tube of 90 SN74HCT08PW
Reel of 2000 SN74HCT08PWR
Reel of 250 SN74HCT08PWT
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
1
SN54HCT08, SN74HCT08
OUTPUT
OUTPUT
UNIT
QUADRUPLE 2-INPUT POSITIVE-AND GATES
SCLS063D – NOVEMBER 1988 – REVISED AUIGUST 2003
FUNCTION TABLE
(each gate)
INPUTS
A B
H H H
L XL
X L L
logic diagram (positive logic)
Y
A
B
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
(VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 2): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
Y
†
DB package 96°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 76°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 3)
SN54HCT08 SN74HCT08
MIN NOM MAX MIN NOM MAX
V
V
V
V
V
∆t/∆v Input transition rise/fall time 500 500 ns
T
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 4.5 5 5.5 4.5 5 5.5 V
CC
High-level input voltage VCC = 4.5 V to 5.5 V 2 2 V
IH
Low-level input voltage VCC = 4.5 V to 5.5 V 0.8 0.8 V
IL
Input voltage 0 V
I
Output voltage 0 V
O
Operating free-air temperature –55 125 –40 85 °C
A
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
CC
CC
0 V
0 V
CC
CC
V
V
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HCT08, SN74HCT08
PARAMETER
TEST CONDITIONS
V
CC
UNIT
V
OH
VI = VIH or V
IL
4.5 V
V
V
OL
VI = VIH or V
IL
4.5 V
V
FROM
TO
PARAMETER
FROM
TO
V
CC
UNIT
tpdA or B
Y
ns
ttY
ns
QUADRUPLE 2-INPUT POSITIVE-AND GATES
SCLS063D – NOVEMBER 1988 – REVISED AUIGUST 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54HCT08 SN74HCT08
MIN TYP MAX MIN MAX MIN MAX
IOH = –20 µA
IOH = –4 mA
IOL = 20 µA
IOL = 4 mA
I
I
I
CC
∆I
CC
C
i
†
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
VI = VCC or 0 5.5 V ±0.1 ±100 ±1000 ±1000 nA
VI = VCC or 0, IO = 0 5.5 V 2 40 20 µA
One input at 0.5 V or 2.4 V,
†
Other inputs at 0 or V
CC
5.5 V 1.4 2.4 3 2.9 mA
4.5 V
to 5.5 V
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
(INPUT)
(OUTPUT)
4.5 V 15 24 35 30
5.5 V 13 22 32 27
4.5 V 9 15 22 19
5.5 V 8 14 20 17
4.4 4.499 4.4 4.4
3.98 4.3 3.7 3.84
0.001 0.1 0.1 0.1
0.17 0.26 0.4 0.33
3 10 10 10 pF
TA = 25°C SN54HCT08 SN74HCT08
MIN TYP MAX MIN MAX MIN MAX
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
Power dissipation capacitance per gate No load 20 pF
pd
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54HCT08, SN74HCT08
3 V
PLH
PHL
QUADRUPLE 2-INPUT POSITIVE-AND GATES
SCLS063D – NOVEMBER 1988 – REVISED AUIGUST 2003
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
LOAD CIRCUIT
Input
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
C. The outputs are measured one at a time with one input transition per measurement.
D. t
2.7 V 2.7 V
t
r
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
and t
Test
Point
CL = 50 pF
(see Note A)
are the same as tpd.
3 V
1.3 V1.3 V
0.3 V0.3 V
0 V
t
f
Figure 1. Load Circuit and Voltage Waveforms
Input
In-Phase
Output
Out-of-Phase
Output
PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
1.3 V
t
PLH
90% 90%
t
PHL
1.3 V 1.3 V
10% 10%
VOLTAGE WAVEFORMS
1.3 V
0 V
t
PHL
V
1.3 V1.3 V
t
r
t
PLH
t
f
OH
10%10%
V
OL
t
f
V
OH
90%90%
V
OL
t
r
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.
Customers should obtain the latest relevant information before placing orders and should verify that such information is current and
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2007, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
PACKAGING INFORMATION
Orderable Device Status
SN74HCT08D ACTIVE SOIC D 14 50 Green (RoHS &
SN74HCT08DBLE OBSOLETE SSOP DB 14 TBD Call TI Call TI
SN74HCT08DBR ACTIVE SSOP DB 14 2000 Green(RoHS &
SN74HCT08DBRE4 ACTIVE SSOP DB 14 2000 Green (RoHS &
SN74HCT08DBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS &
SN74HCT08DE4 ACTIVE SOIC D 14 50 Green (RoHS &
SN74HCT08DG4 ACTIVE SOIC D 14 50 Green (RoHS &
SN74HCT08DR ACTIVE SOIC D 14 2500 Green (RoHS &
SN74HCT08DRE4 ACTIVE SOIC D 14 2500 Green (RoHS &
SN74HCT08DRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
SN74HCT08DT ACTIVE SOIC D 14 250 Green (RoHS &
SN74HCT08DTE4 ACTIVE SOIC D 14 250 Green (RoHS &
SN74HCT08DTG4 ACTIVE SOIC D 14 250 Green (RoHS &
SN74HCT08N ACTIVE PDIP N 14 25 Pb-Free
SN74HCT08NE4 ACTIVE PDIP N 14 25 Pb-Free
SN74HCT08NSR ACTIVE SO NS 14 2000 Green (RoHS &
SN74HCT08NSRE4 ACTIVE SO NS 14 2000 Green (RoHS &
SN74HCT08NSRG4 ACTIVE SO NS 14 2000 Green (RoHS &
SN74HCT08PW ACTIVE TSSOP PW 14 90 Green (RoHS &
SN74HCT08PWE4 ACTIVE TSSOP PW 14 90 Green (RoHS &
SN74HCT08PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS &
SN74HCT08PWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI
SN74HCT08PWR ACTIVE TSSOP PW 14 2000 Green (RoHS &
SN74HCT08PWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS &
SN74HCT08PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS &
SN74HCT08PWT ACTIVE TSSOP PW 14 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
(RoHS)
(RoHS)
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
4-Jun-2007
(3)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
4-Jun-2007
(3)
no Sb/Br)
SN74HCT08PWTE4 ACTIVE TSSOP PW 14 250 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HCT08PWTG4 ACTIVE TSSOP PW 14 250 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
TAPE AND REEL INFORMATION
19-Mar-2008
*All dimensions are nominal
Device Package
SN74HCT08DBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
SN74HCT08DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HCT08DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HCT08NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74HCT08PWR TSSOP PW 14 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm)W(mm)
Pin1
Quadrant
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HCT08DBR SSOP DB 14 2000 346.0 346.0 33.0
SN74HCT08DR SOIC D 14 2500 346.0 346.0 33.0
SN74HCT08DR SOIC D 14 2500 333.2 345.9 28.6
SN74HCT08NSR SO NS 14 2000 346.0 346.0 33.0
SN74HCT08PWR TSSOP PW 14 2000 346.0 346.0 29.0
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,65
28
1
2,00 MAX
0,38
0,22
15
14
A
0,05 MIN
0,15
5,60
5,00
M
8,20
7,40
Seating Plane
0,10
0,25
0,09
0°–ā8°
Gage Plane
0,25
0,95
0,55
PINS **
DIM
A MAX
A MIN
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
14
6,50
6,50
5,905,90
2016
7,50
6,90
24
8,50
28
10,50
9,907,90
30
10,50
9,90
38
12,90
12,30
4040065 /E 12/01
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65
1,20 MAX
14
0,30
0,19
8
4,50
4,30
PINS **
7
Seating Plane
0,15
0,05
8
1
A
DIM
14
0,10
6,60
6,20
M
0,10
0,15 NOM
0°–8°
2016
Gage Plane
24
0,25
0,75
0,50
28
A MAX
A MIN
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
4040064/F 01/97
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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