These devices contain four independent 2-input exclusive-OR gates. They perform the Boolean function
Y = A ę B or Y = A
A common application is as a true/complement element. If one of the inputs is low, the other input is reproduced
in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the
output.
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
B + AB in positive logic.
T
A
PDIP – NTube of 25SN74HC86NSN74HC86N
SOP – NSReel of 2000SN74HC86NSRHC86
CDIP – JTube of 25SNJ54HC86JSNJ54HC86J
CFP – WT ube of 150SNJ54HC86WSNJ54HC86W
LCCC – FKTube of 55SNJ54HC86FKSNJ54HC86FK
ORDERING INFORMATION
PACKAGE
†
Tube of 50SN74HC86D
Reel of 2500SN74HC86DR
Reel of 250SN74HC86DT
Tube of 90SN74HC86PW
Reel of 2000SN74HC86PWR
Reel of 250SN74HC86PWT
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1
SN54HC86, SN74HC86
OUTPUT
OUTPUT
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCLS100E – DECEMBER 1982 – REVISED AUGUST 2003
FUNCTION TABLE
(each gate)
INPUTS
AB
LLL
LHH
HLH
HHL
exclusive-OR logic
An exclusive-OR gate has many applications, some of which can be represented better by alternative logic
symbols.
Exclusive OR
= 1
These are five equivalent exclusive-OR symbols valid for an ’HC86 gate in positive logic; negation may be
shown at any two ports.
Logic Identity ElementEven-Parity ElementOdd-Parity Element
Y
=2k2k + 1
The output is active (low) if
all inputs stand at the same
logic level (i.e., A = B).
The output is active (low) if
an even number of inputs
(i.e., 0 or 2) are active.
The output is active (high) if
an odd number of inputs (i.e.,
only 1 of the 2) are active.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
VI = VCC or 06 V±0.1±100±1000±1000nA
VI = VCC or 0,IO = 06 V24020µA
2 V to 6 V3101010pF
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54HC86, SN74HC86
FROM
TO
PARAMETER
FROM
TO
V
CC
UNIT
tpdA or B
Y
ns
pd
ttY
ns
t
V
PLH
PHL
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCLS100E – DECEMBER 1982 – REVISED AUGUST 2003
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
TA = 25°CSN54HC86SN74HC86
(INPUT)
operating characteristics, TA = 25°C
C
Power dissipation capacitance per gateNo load35pF
pd
PARAMETER MEASUREMENT INFORMATION
(OUTPUT)
2 V40100150125
4.5 V12203025
6 V10172521
2 V287511095
4.5 V8152219
6 V6131916
PARAMETERTEST CONDITIONSTYPUNIT
MINTYPMAXMINMAXMINMAX
From Output
Under Test
LOAD CIRCUIT
Input
NOTES: A. CL includes probe and test-fixture capacitance.
90%90%
t
r
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. The outputs are measured one at a time with one input transition per measurement.
D. t
5962-8404601VCAACTIVECDIPJ141TBDA42 SNPBN / A for Pkg Type
5962-8404601VDAACTIVECFPW141TBDA42N / A for Pkg Type
84046012AACTIVELCCCFK201TBDPOST-PLATE N / A for Pkg Type
8404601CAACTIVECDIPJ141TBDA42SNPBN/ A for Pkg Type
8404601DAACTIVECFPW141TBDA42N / A for Pkg Type
JM38510/65202BCAACTIVECDIPJ141TBDA42 SNPBN / A for Pkg Type
SN54HC86JACTIVECDIPJ141TBDA42 SNPBN / A for Pkg Type
SN74HC86DACTIVESOICD1450Green (RoHS &
SN74HC86DE4ACTIVESOICD1450Green (RoHS &
SN74HC86DG4ACTIVESOICD1450Green (RoHS &
SN74HC86DRACTIVESOICD142500 Green(RoHS &
SN74HC86DRE4ACTIVESOICD142500 Green (RoHS &
SN74HC86DRG4ACTIVESOICD142500 Green(RoHS &
SN74HC86DTACTIVESOICD14250 Green (RoHS &
SN74HC86DTE4ACTIVESOICD14250 Green (RoHS &
SN74HC86DTG4ACTIVESOICD14250 Green (RoHS &
SN74HC86IDRG4Q1ACTIVESOICD142500 Green (RoHS &
SN74HC86NACTIVEPDIPN1425Pb-Free
SN74HC86NE4ACTIVEPDIPN1425Pb-Free
SN74HC86NSRACTIVESONS142000 Green (RoHS &
SN74HC86NSRE4ACTIVESONS142000 Green (RoHS &
SN74HC86NSRG4ACTIVESONS142000 Green(RoHS &
SN74HC86PWACTIVETSSOPPW1490Green (RoHS &
SN74HC86PWE4ACTIVETSSOPPW1490Green (RoHS &
SN74HC86PWG4ACTIVETSSOPPW1490Green (RoHS &
SN74HC86PWLEOBSOLETETSSOPPW14TBDCall TICall TI
SN74HC86PWRACTIVETSSOPPW142000 Green (RoHS &
SN74HC86PWRE4ACTIVETSSOPPW142000 Green (RoHS &
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
(RoHS)
(RoHS)
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAUN / A for Pkg Type
CU NIPDAUN / A for Pkg Type
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
20-Mar-2008
(3)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable DeviceStatus
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
SN74HC86PWRG4ACTIVETSSOPPW142000 Green (RoHS &
Lead/Ball Finish MSL Peak Temp
CU NIPDAULevel-1-260C-UNLIM
20-Mar-2008
(3)
no Sb/Br)
SN74HC86PWTACTIVETSSOPPW14250 Green (RoHS &
CU NIPDAULevel-1-260C-UNLIM
no Sb/Br)
SN74HC86PWTE4ACTIVETSSOPPW14250 Green (RoHS &
CU NIPDAULevel-1-260C-UNLIM
no Sb/Br)
SN74HC86PWTG4ACTIVETSSOPPW14250 Green (RoHS &
CU NIPDAULevel-1-260C-UNLIM
no Sb/Br)
SN74HC86QDRG4Q1ACTIVESOICD142500 Green (RoHS &
CU NIPDAULevel-1-260C-UNLIM
no Sb/Br)
SNJ54HC86FKACTIVELCCCFK201TBDPOST-PLATE N / A for Pkg Type
SNJ54HC86JACTIVECDIPJ141TBDA42 SNPBN / A for Pkg Type
SNJ54HC86WACTIVECFPW141TBDA42N / A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
4040140/D 10/96
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65
1,20 MAX
14
0,30
0,19
8
4,50
4,30
PINS **
7
Seating Plane
0,15
0,05
8
1
A
DIM
14
0,10
6,60
6,20
M
0,10
0,15 NOM
0°–8°
2016
Gage Plane
24
0,25
0,75
0,50
28
A MAX
A MIN
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
4040064/F 01/97
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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