D
SOIC – D
HC86
–40°C to 85°C
TSSOP – PW
HC86
–55°C to 125°C
f
Wide Operating Voltage Range of 2 V to 6 V
D
Outputs Can Drive Up To 10 LSTTL Loads
D
Low Power Consumption, 20-µA Max I
D
Typical t
SN74HC86 . . . D, N, NS, OR PW PACKAGE
= 10 ns
pd
SN54HC86 ...J OR W PACKAGE
(TOP VIEW)
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
14
13
12
11
10
V
CC
4B
4A
4Y
3B
9
3A
8
3Y
CC
SN54HC86, SN74HC86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCLS100E – DECEMBER 1982 – REVISED AUGUST 2003
D
±4-mA Output Drive at 5 V
D
Low Input Current of 1 µA Max
D
True Logic
SN54HC86 . . . FK PACKAGE
1Y
NC
2A
NC
2B
NC – No internal connection
(TOP VIEW)
1B1ANC
3212019
4
5
6
7
8
910111213
2Y
NC
GND
CC
V
3Y
4B
18
17
16
15
14
3A
4A
NC
4Y
NC
3B
description/ordering information
These devices contain four independent 2-input exclusive-OR gates. They perform the Boolean function
Y = A ę B or Y = A
A common application is as a true/complement element. If one of the inputs is low, the other input is reproduced
in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the
output.
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
B + AB in positive logic.
T
A
PDIP – N Tube of 25 SN74HC86N SN74HC86N
SOP – NS Reel of 2000 SN74HC86NSR HC86
CDIP – J Tube of 25 SNJ54HC86J SNJ54HC86J
CFP – W T ube of 150 SNJ54HC86W SNJ54HC86W
LCCC – FK Tube of 55 SNJ54HC86FK SNJ54HC86FK
ORDERING INFORMATION
PACKAGE
†
Tube of 50 SN74HC86D
Reel of 2500 SN74HC86DR
Reel of 250 SN74HC86DT
Tube of 90 SN74HC86PW
Reel of 2000 SN74HC86PWR
Reel of 250 SN74HC86PWT
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1
SN54HC86, SN74HC86
OUTPUT
OUTPUT
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCLS100E – DECEMBER 1982 – REVISED AUGUST 2003
FUNCTION TABLE
(each gate)
INPUTS
A B
L L L
L HH
H LH
H H L
exclusive-OR logic
An exclusive-OR gate has many applications, some of which can be represented better by alternative logic
symbols.
Exclusive OR
= 1
These are five equivalent exclusive-OR symbols valid for an ’HC86 gate in positive logic; negation may be
shown at any two ports.
Logic Identity Element Even-Parity Element Odd-Parity Element
Y
= 2k 2k + 1
The output is active (low) if
all inputs stand at the same
logic level (i.e., A = B).
The output is active (low) if
an even number of inputs
(i.e., 0 or 2) are active.
The output is active (high) if
an odd number of inputs (i.e.,
only 1 of the 2) are active.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
(VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 2): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 76°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
†
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC86, SN74HC86
UNIT
VIHHigh-level input voltage
V
IH
VILLow-level input voltage
V
IL
v
Input transition rise/fall time
ns
PARAMETER
TEST CONDITIONS
V
CC
UNIT
IOH = –20 µA
V
OH
VI = VIH or V
IL
OH
V
OH
IIH IL
IOL = 20 µA
V
OL
VI = VIH or V
IL
OL
V
OL
IIH IL
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCLS100E – DECEMBER 1982 – REVISED AUGUST 2003
recommended operating conditions (see Note 3)
SN54HC86 SN74HC86
MIN NOM MAX MIN NOM MAX
V
V
V
∆t/∆
T
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 2 5 6 2 5 6 V
CC
VCC = 2 V 1.5 1.5
VCC = 4.5 V 3.15 3.15
VCC = 6 V 4.2 4.2
VCC = 2 V 0.5 0.5
VCC = 4.5 V 1.35 1.35
VCC = 6 V 1.8 1.8
Input voltage 0 V
I
Output voltage 0 V
O
VCC = 2 V 1000 1000
VCC = 4.5 V 500 500
VCC = 6 V 400 400
Operating free-air temperature –55 125 –40 85 °C
A
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
CC
CC
0 V
0 V
CC
CC
V
V
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54HC86 SN74HC86
MIN TYP MAX MIN MAX MIN MAX
2 V 1.9 1.998 1.9 1.9
4.5 V 4.4 4.499 4.4 4.4
6 V 5.9 5.999 5.9 5.9
IOH = –4 mA 4.5 V 3.98 4.3 3.7 3.84
IOH = –5.2 mA 6 V 5.48 5.8 5.2 5.34
2 V 0.002 0.1 0.1 0.1
4.5 V 0.001 0.1 0.1 0.1
6 V 0.001 0.1 0.1 0.1
IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33
IOL = 5.2 mA 6 V 0.15 0.26 0.4 0.33
I
I
C
I
CC
i
VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
VI = VCC or 0, IO = 0 6 V 2 40 20 µA
2 V to 6 V 3 10 10 10 pF
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54HC86, SN74HC86
FROM
TO
PARAMETER
FROM
TO
V
CC
UNIT
tpdA or B
Y
ns
pd
ttY
ns
t
V
PLH
PHL
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCLS100E – DECEMBER 1982 – REVISED AUGUST 2003
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54HC86 SN74HC86
(INPUT)
operating characteristics, TA = 25°C
C
Power dissipation capacitance per gate No load 35 pF
pd
PARAMETER MEASUREMENT INFORMATION
(OUTPUT)
2 V 40 100 150 125
4.5 V 12 20 30 25
6 V 10 17 25 21
2 V 28 75 110 95
4.5 V 8 15 22 19
6 V 6 13 19 16
PARAMETER TEST CONDITIONS TYP UNIT
MIN TYP MAX MIN MAX MIN MAX
From Output
Under Test
LOAD CIRCUIT
Input
NOTES: A. CL includes probe and test-fixture capacitance.
90% 90%
t
r
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. The outputs are measured one at a time with one input transition per measurement.
D. t
and t
Test
Point
CL = 50 pF
(see Note A)
50%50%
are the same as tpd.
V
CC
10%10%
0 V
t
f
Figure 1. Load Circuit and Voltage Waveforms
Input
In-Phase
Output
Out-of-Phase
Output
50%
t
PLH
90% 90%
t
PHL
50% 50%
10% 10%
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
VOLTAGE WAVEFORMS
50%
t
PHL
50%50%
t
r
t
PLH
t
f
CC
0 V
V
OH
10%10%
V
OL
t
f
V
OH
90%90%
V
OL
t
r
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,
improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.
Customers should obtain the latest relevant information before placing orders and should verify that such information is current and
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
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Wireless
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Wireless www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2007, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
PACKAGING INFORMATION
Orderable Device Status
5962-8404601VCA ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type
5962-8404601VDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type
84046012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
8404601CA ACTIVE CDIP J 14 1 TBD A42SNPB N/ A for Pkg Type
8404601DA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type
JM38510/65202BCA ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type
SN54HC86J ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type
SN74HC86D ACTIVE SOIC D 14 50 Green (RoHS &
SN74HC86DE4 ACTIVE SOIC D 14 50 Green (RoHS &
SN74HC86DG4 ACTIVE SOIC D 14 50 Green (RoHS &
SN74HC86DR ACTIVE SOIC D 14 2500 Green(RoHS &
SN74HC86DRE4 ACTIVE SOIC D 14 2500 Green (RoHS &
SN74HC86DRG4 ACTIVE SOIC D 14 2500 Green(RoHS &
SN74HC86DT ACTIVE SOIC D 14 250 Green (RoHS &
SN74HC86DTE4 ACTIVE SOIC D 14 250 Green (RoHS &
SN74HC86DTG4 ACTIVE SOIC D 14 250 Green (RoHS &
SN74HC86IDRG4Q1 ACTIVE SOIC D 14 2500 Green (RoHS &
SN74HC86N ACTIVE PDIP N 14 25 Pb-Free
SN74HC86NE4 ACTIVE PDIP N 14 25 Pb-Free
SN74HC86NSR ACTIVE SO NS 14 2000 Green (RoHS &
SN74HC86NSRE4 ACTIVE SO NS 14 2000 Green (RoHS &
SN74HC86NSRG4 ACTIVE SO NS 14 2000 Green(RoHS &
SN74HC86PW ACTIVE TSSOP PW 14 90 Green (RoHS &
SN74HC86PWE4 ACTIVE TSSOP PW 14 90 Green (RoHS &
SN74HC86PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS &
SN74HC86PWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI
SN74HC86PWR ACTIVE TSSOP PW 14 2000 Green (RoHS &
SN74HC86PWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS &
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
(RoHS)
(RoHS)
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
20-Mar-2008
(3)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
SN74HC86PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS &
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-1-260C-UNLIM
20-Mar-2008
(3)
no Sb/Br)
SN74HC86PWT ACTIVE TSSOP PW 14 250 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC86PWTE4 ACTIVE TSSOP PW 14 250 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC86PWTG4 ACTIVE TSSOP PW 14 250 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC86QDRG4Q1 ACTIVE SOIC D 14 2500 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SNJ54HC86FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
SNJ54HC86J ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type
SNJ54HC86W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
TAPE AND REEL INFORMATION
19-Mar-2008
*All dimensions are nominal
Device Package
SN74HC86DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC86DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC86NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74HC86PWR TSSOP PW 14 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm)W(mm)
Pin1
Quadrant
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HC86DR SOIC D 14 2500 346.0 346.0 33.0
SN74HC86DR SOIC D 14 2500 333.2 345.9 28.6
SN74HC86NSR SO NS 14 2000 346.0 346.0 33.0
SN74HC86PWR TSSOP PW 14 2000 346.0 346.0 29.0
Pack Materials-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A SQ
B SQ
19
20
21
22
23
24
25
12826 27
12
1314151618 17
0.020 (0,51)
0.010 (0,25)
MIN
0.342
(8,69)
0.442
0.640
0.739
0.938
1.141
A
0.358
(9,09)
0.458
(11,63)
0.660
(16,76)
0.761
(19,32)(18,78)
0.962
(24,43)
1.165
(29,59)
NO. OF
TERMINALS
**
11
10
9
8
7
6
5
432
20
28
44
52
68
84
0.020 (0,51)
0.010 (0,25)
(11,23)
(16,26)
(23,83)
(28,99)
MINMAX
0.307
(7,80)
0.406
(10,31)
0.495
(12,58)
0.495
(12,58)
0.850
(21,6)
1.047
(26,6)
0.080 (2,03)
0.064 (1,63)
B
MAX
0.358
(9,09)
0.458
(11,63)
0.560
(14,22)
0.560
(14,22)
0.858
(21,8)
1.063
(27,0)
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
4040140/D 10/96
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65
1,20 MAX
14
0,30
0,19
8
4,50
4,30
PINS **
7
Seating Plane
0,15
0,05
8
1
A
DIM
14
0,10
6,60
6,20
M
0,10
0,15 NOM
0°–8°
2016
Gage Plane
24
0,25
0,75
0,50
28
A MAX
A MIN
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
4040064/F 01/97
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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