TEXAS INSTRUMENTS SN54HC74, SN74HC74 Technical data

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SN54HC74, SN74HC74

DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS

WITH CLEAR AND PRESET

SCLS094D – DECEMBER 1982 – REVISED JUL Y 2003

D

Wide Operating Voltage Range of 2 V to 6 V

D

Outputs Can Drive Up To 10 LSTTL Loads

D

Low Power Consumption, 40-µA Max I

D

Typical t

D

±4-mA Output Drive at 5 V

D

Low Input Current of 1 µA Max

pd

= 15 ns

description/ordering information

The ’HC74 devices contain two independent
D-type positive-edge-triggered flip-flops. A low
level at the preset (PRE
or resets the outputs, regardless of the levels of
the other inputs. When PRE
(high), data at the data (D) input meeting the setup
time requirements are transferred to the outputs
on the positive-going edge of the clock (CLK)
pulse. Clock triggering occurs at a voltage level
and is not directly related to the rise time of CLK.
Following the hold-time interval, data at the
D input can be changed without affecting the
levels at the outputs.

) or clear (CLR) inputs sets

and CLR are inactive

CC

SN54HC74 ...J OR W PACKAGE

SN74HC74 . . . D, DB, N, NS, OR PW PACKAGE

1CLR

1CLK
1PRE

GND

SN54HC74 . . . FK PACKAGE

1CLK

NC

1PRE

NC

1Q

(TOP VIEW)

1

1D

2
3
4
5

1Q

6

1Q

7

(TOP VIEW)

1D

1CLR

3212019

4
5
6
7
8

910111213

NC

14
13
12
11
10

9
8

V

CC

V

CC

2CLR
2D
2CLK
2PRE
2Q
2Q

2CLR

18
17
16
15
14

2D
NC
2CLK
NC
2PRE

1Q

NC – No internal connection

GND

NC

2Q

2Q

ORDERING INFORMA TION

T

A

PDIP – N Tube of 25 SN74HC74N SN74HC74N

SOIC – D

–40°C to 85°C

–55°C to 125°C

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.

SOP – NS Reel of 2000 SN74HC74NSR HC74
SSOP – DB Reel of 2000 SN74HC74DBR HC74

TSSOP – PW

CDIP – J Tube of 25 SNJ54HC74J SNJ54HC74J
CFP – W T ube of 150 SNJ54HC74W SNJ54HC74W
LCCC – FK Tube of 55 SNJ54HC74FK SNJ54HC74FK

PACKAGE

†

Tube of 50 SN74HC74D
Reel of 2500 SN74HC74DR
Reel of 250 SN74HC74DT

Tube of 90 SN74HC74PW
Reel of 2000 SN74HC74PWR
Reel of 250 SN74HC74PWT

ORDERABLE

PART NUMBER

TOP-SIDE
MARKING

HC74

HC74

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  2003, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.

1

SN54HC74, SN74HC74
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET

SCLS094D – DECEMBER 1982 – REVISED JULY 2003

FUNCTION TABLE

INPUTS OUTPUTS

PRE CLR CLK D Q Q

L H X X H L
H LXXLH
L LXXH†H
H H ↑ HHL
H H ↑ LLH

logic diagram (positive logic)

PRE

H H L X Q

†

This configuration is nonstable; that is, it does not
persist when PRE
(high) level.

or CLR returns to its inactive

0

†

Q

0

CLK

CLR

C

C

C

D

TG

C

C

TG

C

C

TG

C

C

TG

C

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ

Storage temperature range, T

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

(VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OK

(VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 2): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

DB package 96°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NS package 76°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

Q

Q

‡

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UNIT

PARAMETER

TEST CONDITIONS

V

UNIT

SN54HC74, SN74HC74

DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS

WITH CLEAR AND PRESET

SCLS094D – DECEMBER 1982 – REVISED JULY 2003

recommended operating conditions (see Note 3)

SN54HC74 SN74HC74

MIN NOM MAX MIN NOM MAX

V

V

V

V
V

∆t/∆v Input transition rise/fall time

T

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Supply voltage 2 5 6 2 5 6 V

CC

VCC = 2 V 1.5 1.5

High-level input voltage

IH

Low-level input voltage

IL

Input voltage 0 V

I

Output voltage 0 V

O

Operating free-air temperature –55 125 –40 85 °C

A

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

VCC = 4.5 V
VCC = 6 V 4.2 4.2
VCC = 2 V 0.5 0.5
VCC = 4.5 V
VCC = 6 V 1.8 1.8

VCC = 2 V 1000 1000
VCC = 4.5 V
VCC = 6 V 400 400

3.15 3.15

1.35 1.35

CC
CC

500 500

0 V
0 V

CC
CC

V

V

V
V

ns

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

TA = 25°C SN54HC74 SN74HC74

MIN TYP MAX MIN MAX MIN MAX

V

V

V

V

I
I
C

OH

OL

I
CC

i

CC

2 V 1.9 1.998 1.9 1.9

IOH = –20 µA

VI = VIH or V

VI = VIH or V

VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
VI = VCC or 0, IO = 0 6 V 4 80 40 µA

IL

IOH = –4 mA 4.5 V 3.98 4.3 3.7 3.84
IOH = –5.2 mA 6 V 5.48 5.8 5.2 5.34

IOL = 20 µA

IL

IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33
IOL = 5.2 mA 6 V 0.15 0.26 0.4 0.33

4.5 V 4.4 4.499 4.4 4.4
6 V 5.9 5.999 5.9 5.9

2 V 0.002 0.1 0.1 0.1

4.5 V 0.001 0.1 0.1 0.1
6 V 0.001 0.1 0.1 0.1

2 V to 6 V 3 10 10 10 pF

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3

SN54HC74, SN74HC74

V

UNIT

twPulse duration

ns

tsuSetup time before CLK↑

ns

↑

PARAMETER

V

UNIT

t

ns

DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET

SCLS094D – DECEMBER 1982 – REVISED JULY 2003

timing requirements over recommended operating free-air temperature range (unless otherwise
noted)

TA = 25°C SN54HC74 SN74HC74

CC

MIN MAX MIN MAX MIN MAX

2 V 6 4.2 5

f

clock

t

h

Clock frequency

p

Hold time, data after CLK

PRE or CLR low

CLK high or low

Data

PRE or CLR inactive

4.5 V
6 V 0 36 0 25 0 29
2 V 100 150 125

4.5 V 20 30 25
6 V 17 25 21
2 V 80 120 100

4.5 V 16 24 20
6 V 14 20 17
2 V 100 150 125

4.5 V 20 30 25
6 V 17 25 21
2 V 25 40 30

4.5 V 5 8 6
6 V 4 7 5
2 V 0 0 0

4.5 V 0 0 0
6 V 0 0 0

31 21 25

MHz

ns

switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)

TA = 25°C SN54HC74 SN74HC74

MIN TYP MAX MIN MAX MIN MAX

MHz

ns

f

max

pd

t

t

FROM TO

(INPUT) (OUTPUT)

PRE or CLR Q or Q

CLK Q or Q

Q or Q

CC

2 V 6 10 4.2 5

4.5 V 31 50 21 25
6 V 36 60 25 29
2 V 70 230 345 290

4.5 V 20 46 69 58
6 V 15 39 59 49
2 V 70 175 250 220

4.5 V 20 35 50 44
6 V 15 30 42 37
2 V 28 75 110 95

4.5 V 8 15 22 19
6 V 6 13 19 16

operating characteristics, TA = 25°C

PARAMETER TEST CONDITIONS TYP UNIT

C

Power dissipation capacitance per flip-flop No load 35 pF

pd

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54HC74, SN74HC74

DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS

WITH CLEAR AND PRESET

SCLS094D – DECEMBER 1982 – REVISED JULY 2003

PARAMETER MEASUREMENT INFORMATION

V

0 V

V

0 V

CC

CC

From Output

Under Test

LOAD CIRCUIT

Test
Point

CL = 50 pF
(see Note A)

High-Level

Pulse

Low-Level

Pulse

50%

t

w

50%

VOLTAGE WAVEFORMS

PULSE DURATIONS

50%

50%

Reference

Input

t

su

Data

Input

SETUP AND HOLD AND INPUT RISE AND FALL TIMES

NOTES: A. CL includes probe and test-fixture capacitance.

B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following

characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. For clock inputs, f
D. The outputs are measured one at a time with one input transition per measurement.
E. t

PLH

90% 90%

VOLTAGE WAVEFORMS

and t

PHL

50%

t

h

t

r

is measured when the input duty cycle is 50%.

max

are the same as tpd.

50%50%

10%10%

t

f

Figure 1. Load Circuit and Voltage Waveforms

V

0 V

V

0 V

CC

CC

Input

In-Phase

Output

Out-of-Phase

Output

PROPAGATION DELAY AND OUTPUT TRANSITION TIMES

50%

t

PLH

90% 90%

t

PHL

50% 50%

10% 10%

VOLTAGE WAVEFORMS

V

50%

t

PHL

50%50%

t

r

t

PLH

t

f

CC

0 V

V

OH

10%10%

V

OL

t

f

V

OH

90%90%

V

OL

t

r

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5