TEXAS INSTRUMENTS SN54HC74, SN74HC74 Technical data

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SN54HC74, SN74HC74
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS094D – DECEMBER 1982 – REVISED JUL Y 2003
D
D
Outputs Can Drive Up To 10 LSTTL Loads
D
Low Power Consumption, 40-µA Max I
D
Typical t
D
±4-mA Output Drive at 5 V
D
Low Input Current of 1 µA Max
pd
= 15 ns
description/ordering information
The ’HC74 devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset (PRE or resets the outputs, regardless of the levels of the other inputs. When PRE (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
) or clear (CLR) inputs sets
and CLR are inactive
CC
SN54HC74 ...J OR W PACKAGE
SN74HC74 . . . D, DB, N, NS, OR PW PACKAGE
1CLR
1CLK 1PRE
GND
SN54HC74 . . . FK PACKAGE
1CLK
NC
1PRE
NC
1Q
(TOP VIEW)
1
1D
2 3 4 5
1Q
6
1Q
7
(TOP VIEW)
1D
1CLR
3212019
4 5 6 7 8
910111213
NC
14 13 12 11 10
9 8
V
CC
V
CC
2CLR 2D 2CLK 2PRE 2Q 2Q
2CLR
18 17 16 15 14
2D NC 2CLK NC 2PRE
1Q
NC – No internal connection
GND
NC
2Q
2Q
ORDERING INFORMA TION
T
A
PDIP – N Tube of 25 SN74HC74N SN74HC74N
SOIC – D
–40°C to 85°C
–55°C to 125°C
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
SOP – NS Reel of 2000 SN74HC74NSR HC74 SSOP – DB Reel of 2000 SN74HC74DBR HC74
TSSOP – PW
CDIP – J Tube of 25 SNJ54HC74J SNJ54HC74J CFP – W T ube of 150 SNJ54HC74W SNJ54HC74W LCCC – FK Tube of 55 SNJ54HC74FK SNJ54HC74FK
PACKAGE
Tube of 50 SN74HC74D Reel of 2500 SN74HC74DR Reel of 250 SN74HC74DT
Tube of 90 SN74HC74PW Reel of 2000 SN74HC74PWR Reel of 250 SN74HC74PWT
ORDERABLE
PART NUMBER
TOP-SIDE MARKING
HC74
HC74
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
1
SN54HC74, SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SCLS094D – DECEMBER 1982 – REVISED JULY 2003
FUNCTION TABLE
INPUTS OUTPUTS
PRE CLR CLK D Q Q
L H X X H L H LXXLH L LXXH†H H H HHL H H LLH
logic diagram (positive logic)
PRE
H H L X Q
This configuration is nonstable; that is, it does not persist when PRE (high) level.
or CLR returns to its inactive
0
Q
0
CLK
CLR
C
C
C
D
TG
C
C
TG
C
C
TG
C
C
TG
C
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V Input clamp current, I Output clamp current, I Continuous output current, I Continuous current through V Package thermal impedance, θ
Storage temperature range, T
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
(VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 2): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DB package 96°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 76°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
Q
Q
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
UNIT
PARAMETER
TEST CONDITIONS
V
UNIT
SN54HC74, SN74HC74
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS094D – DECEMBER 1982 – REVISED JULY 2003
recommended operating conditions (see Note 3)
SN54HC74 SN74HC74
MIN NOM MAX MIN NOM MAX
V
V
V
V V
t/v Input transition rise/fall time
T
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 2 5 6 2 5 6 V
CC
VCC = 2 V 1.5 1.5
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 V
I
Output voltage 0 V
O
Operating free-air temperature –55 125 –40 85 °C
A
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
VCC = 4.5 V VCC = 6 V 4.2 4.2 VCC = 2 V 0.5 0.5 VCC = 4.5 V VCC = 6 V 1.8 1.8
VCC = 2 V 1000 1000 VCC = 4.5 V VCC = 6 V 400 400
3.15 3.15
1.35 1.35
CC CC
500 500
0 V 0 V
CC CC
V
V
V V
ns
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C SN54HC74 SN74HC74
MIN TYP MAX MIN MAX MIN MAX
V
V
V
V
I I C
OH
OL
I CC
i
CC
2 V 1.9 1.998 1.9 1.9
IOH = –20 µA
VI = VIH or V
VI = VIH or V
VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA VI = VCC or 0, IO = 0 6 V 4 80 40 µA
IL
IOH = –4 mA 4.5 V 3.98 4.3 3.7 3.84 IOH = –5.2 mA 6 V 5.48 5.8 5.2 5.34
IOL = 20 µA
IL
IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33 IOL = 5.2 mA 6 V 0.15 0.26 0.4 0.33
4.5 V 4.4 4.499 4.4 4.4 6 V 5.9 5.999 5.9 5.9
2 V 0.002 0.1 0.1 0.1
4.5 V 0.001 0.1 0.1 0.1 6 V 0.001 0.1 0.1 0.1
2 V to 6 V 3 10 10 10 pF
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3
SN54HC74, SN74HC74
V
UNIT
twPulse duration
ns
tsuSetup time before CLK
ns
PARAMETER
V
UNIT
t
ns
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SCLS094D – DECEMBER 1982 – REVISED JULY 2003
timing requirements over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C SN54HC74 SN74HC74
CC
MIN MAX MIN MAX MIN MAX
2 V 6 4.2 5
f
clock
t
h
Clock frequency
p
Hold time, data after CLK
PRE or CLR low
CLK high or low
Data
PRE or CLR inactive
4.5 V 6 V 0 36 0 25 0 29 2 V 100 150 125
4.5 V 20 30 25 6 V 17 25 21 2 V 80 120 100
4.5 V 16 24 20 6 V 14 20 17 2 V 100 150 125
4.5 V 20 30 25 6 V 17 25 21 2 V 25 40 30
4.5 V 5 8 6 6 V 4 7 5 2 V 0 0 0
4.5 V 0 0 0 6 V 0 0 0
31 21 25
MHz
ns
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
TA = 25°C SN54HC74 SN74HC74
MIN TYP MAX MIN MAX MIN MAX
MHz
ns
f
max
pd
t
t
FROM TO
(INPUT) (OUTPUT)
PRE or CLR Q or Q
CLK Q or Q
Q or Q
CC
2 V 6 10 4.2 5
4.5 V 31 50 21 25 6 V 36 60 25 29 2 V 70 230 345 290
4.5 V 20 46 69 58 6 V 15 39 59 49 2 V 70 175 250 220
4.5 V 20 35 50 44 6 V 15 30 42 37 2 V 28 75 110 95
4.5 V 8 15 22 19 6 V 6 13 19 16
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
Power dissipation capacitance per flip-flop No load 35 pF
pd
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
SN54HC74, SN74HC74
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS094D – DECEMBER 1982 – REVISED JULY 2003
PARAMETER MEASUREMENT INFORMATION
V
0 V
V
0 V
CC
CC
From Output
Under Test
LOAD CIRCUIT
Test Point
CL = 50 pF (see Note A)
High-Level
Pulse
Low-Level
Pulse
50%
t
w
50%
VOLTAGE WAVEFORMS
PULSE DURATIONS
50%
50%
Reference
Input
t
su
Data
Input
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. For clock inputs, f D. The outputs are measured one at a time with one input transition per measurement. E. t
PLH
90% 90%
VOLTAGE WAVEFORMS
and t
PHL
50%
t
h
t
r
is measured when the input duty cycle is 50%.
max
are the same as tpd.
50%50%
10%10%
t
f
Figure 1. Load Circuit and Voltage Waveforms
V
0 V
V
0 V
CC
CC
Input
In-Phase
Output
Out-of-Phase
Output
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
t
PLH
90% 90%
t
PHL
50% 50%
10% 10%
VOLTAGE WAVEFORMS
V
50%
t
PHL
50%50%
t
r
t
PLH
t
f
CC
0 V
V
OH
10%10%
V
OL
t
f
V
OH
90%90%
V
OL
t
r
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
5
PACKAGE OPTION ADDENDUM
www.ti.com
8-Mar-2005
PACKAGING INFORMATION
Orderable Device Status
(1)
Package
Type
Package Drawing
Pins Package
Qty
Eco Plan
5962-8405601VCA ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC 5962-8405601VDA ACTIVE CFP W 14 1 None Call TI Level-NC-NC-NC
84056012A ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC 8405601CA ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC
8405601DA ACTIVE CFP W 14 1 None Call TI Level-NC-NC-NC JM38510/65302B2A ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC JM38510/65302BCA ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC JM38510/65302BDA ACTIVE CFP W 14 1 None Call TI Level-NC-NC-NC
SN54HC74J ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC
SN74HC74ADBLE OBSOLETE SSOP DB 14 None Call TI Call TI
SN74HC74D ACTIVE SOIC D 14 50 Pb-Free
SN74HC74DBLE OBSOLETE SSOP DB 14 None Call TI Call TI
SN74HC74DBR ACTIVE SSOP DB 14 2000 Pb-Free
SN74HC74DR ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br)
SN74HC74DT ACTIVE SOIC D 14 250 Pb-Free
SN74HC74N ACTIVE PDIP N 14 25 Pb-Free
SN74HC74N3 OBSOLETE PDIP N 14 None Call TI Call TI
SN74HC74NSR ACTIVE SO NS 14 2000 Pb-Free
SN74HC74PW ACTIVE TSSOP PW 14 90 Pb-Free
SN74HC74PWLE OBSOLETE TSSOP PW 14 None Call TI Call TI
SN74HC74PWR ACTIVE TSSOP PW 14 2000 Pb-Free
SN74HC74PWT ACTIVE TSSOP PW 14 250 Pb-Free
SNJ54HC74FK ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC
SNJ54HC74J ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC
SNJ54HC74W ACTIVE CFP W 14 1 None Call TI Level-NC-NC-NC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(RoHS)
(RoHS)
(RoHS)
(RoHS)
(RoHS)
(RoHS)
(RoHS)
(RoHS)
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
CU NIPDAU Level-NC-NC-NC
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
CU NIPDAU Level-1-250C-UNLIM
CU NIPDAU Level-1-250C-UNLIM
CU NIPDAU Level-1-250C-UNLIM
(3)
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
8-Mar-2005
Addendum-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A SQ
B SQ
20
22
23
24
25
19
21
12826 27
12
1314151618 17
0.020 (0,51)
0.010 (0,25)
MIN
0.342
(8,69)
0.442
0.640
0.739
0.938
1.141
A
(11,63)
(16,76)
(19,32)(18,78)
(24,43)
(29,59)
0.358
(9,09)
0.458 (10,31)
0.660 (12,58)
0.761 (12,58)
0.962
1.165
NO. OF
TERMINALS
**
11
10
9
8
7
6
5
432
20
28
44
52
68
84
0.020 (0,51)
0.010 (0,25)
(11,23)
(16,26)
(23,83)
(28,99)
MINMAX
0.307
(7,80)
0.406
0.495
0.495
0.850
(21,6)
1.047
(26,6)
0.080 (2,03)
0.064 (1,63)
B
MAX
0.358
(9,09)
0.458
(11,63)
0.560
(14,22)
0.560
(14,22)
0.858 (21,8)
1.063 (27,0)
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
4040140/D 10/96
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,65
28
1
2,00 MAX
0,38 0,22
15
14
A
0,05 MIN
0,15
5,60 5,00
M
8,20 7,40
Seating Plane
0,10
0,25 0,09
0°ā8°
Gage Plane
0,25
0,95 0,55
PINS **
DIM
A MAX
A MIN
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150
14
6,50
6,50
5,905,90
2016
7,50
6,90
24
8,50
28
10,50
9,907,90
30
10,50
9,90
38
12,90
12,30
4040065 /E 12/01
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65
1,20 MAX
14
0,30 0,19
8
4,50 4,30
PINS **
7
Seating Plane
0,15 0,05
8
1
A
DIM
14
0,10
6,60 6,20
M
0,10
0,15 NOM
0°–8°
2016
Gage Plane
24
0,25
0,75 0,50
28
A MAX
A MIN
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
4040064/F 01/97
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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