SN54HC574, SN74HC574
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS148C – DECEMBER 1982 – REVISED JANUARY 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
High-Current 3-State Noninverting Outputs
Drive Bus Lines Directly or up to 15 LSTTL
Loads
D
Bus-Structured Pinout
D
Package Options Include Plastic
Small-Outline (DW), Thin Shrink
Small-Outline (PW), and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs
description
These octal edge-triggered D-type flip-flops
feature 3-state outputs designed specifically for
bus driving. They are particularly suitable for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
The eight flip-flops enter data on the low-to-high
transition of the clock (CLK) input.
A buffered output-enable (OE
) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
increased drive provide the capability to drive bus
lines without interface or pullup components.
OE
does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The SN54HC574 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74HC574 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
OE CLK D
Q
L ↑ H H
L ↑ LL
L H or L X Q
0
H X X Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
3212019
910111213
4
5
6
7
8
18
17
16
15
14
2Q
3Q
4Q
5Q
6Q
3D
4D
5D
6D
7D
2D1DOE
8Q
7Q
V
1Q
8D
GND
CLK
SN54HC574 . . . FK PACKAGE
(TOP VIEW)
CC
SN54HC574 ...J OR W PACKAGE
SN74HC574 ...DW, N, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLK
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.