Texas Instruments SN54HC42J, SN74HC42D, SN74HC42DR, SN74HC42N, SNJ54HC42FK Datasheet
...
NO
Invalid
SN54HC42, SN74HC42
4-LINE TO 10-LINE DECODERS (1 of 10)
SCLS091B – DECEMBER 1982 – REVISED MA Y 1997
D
Full Decoding of Input Logic
D
All Outputs Are High for Invalid BCD
Conditions
D
Also for Applications as 3-Line to 8-Line
Decoders
D
Package Options Include Plastic
Small-Outline (D) and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs
description
These monolithic decimal decoders consist of
eight inverters and ten 4-input NAND gates. The
inverters are connected in pairs to make BCD
input data available for decoding by the NAND
gates. Full decoding of valid input logic ensures
that all inputs remain off for all invalid input
conditions.
The SN54HC42 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74HC42 is characterized for
operation from –40°C to 85°C.
.
D C B A 0 1 2 3 4 5 6 7 8 9
0 L L L L L H H H H H H H H H
1 L LLHHLHHHHHHHH
2 L LHLHHLHHHHHHH
3 L LHHHHHLHHHHHH
4 L HLLHHHHLHHHHH
5 L H L H H H H H H L H H H H
6 L HHLHHHHHHLHHH
7 L HHHHHHHHHHLHH
8 H LLLHHHHHHHHLH
9 H LLHHHHHHHHHHL
H L H L H H H H H H H H H H
H LHHHHHHHHHHHH
H HLLHHHHHHHHHH
H HLHHHHHHHHHHH
H HHLHHHHHHHHHH
H H H H H H H H H H H H H H
INPUTS OUTPUTS
FUNCTION TABLE
SN54HC42 . . . J OR W PACKAGE
SN74HC42 ...D OR N PACKAGE
SN54HC42 . . . FK PACKAGE
2
3
NC
4
5
NC – No internal connection
(TOP VIEW)
0
1
1
2
2
3
3
4
5
4
6
5
7
6
GND
8
(TOP VIEW)
10NC
3212019
4
5
6
7
8
910111213
6
GND
NC
16
15
14
13
12
11
10
9
V
7
CC
A
18
17
16
15
14
8
V
CC
A
B
C
D
9
8
7
B
C
NC
D
9
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
SN54HC42, SN74HC42
4-LINE TO 10-LINE DECODERS (1 of 10)
SCLS091B – DECEMBER 1982 – REVISED MA Y 1997
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, N, and W packages.
†
BCD/DEC
0
1
15
A
14
B
13
C
12
D
1
2
4
8
2
3
4
5
6
7
8
9
logic diagram (positive logic)
15
A
10
11
1
0
2
1
3
2
4
3
5
4
6
5
7
6
9
7
8
9
1
0
2
1
14
B
13
C
12
D
Pin numbers shown are for the D, J, N, and W packages.
10
11
3
2
4
3
5
4
6
5
7
6
9
7
8
9
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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