SN54HC393, SN74HC393
DUAL 4-BIT BINARY COUNTERS
SCLS143B – DECEMBER 1982 – REVISED MA Y 1997
D
Dual 4-Bit Binary Counters With Individual
Clocks
D
Direct Clear for Each 4-Bit Counter
D
Can Significantly Improve System
Densities by Reducing Counter Package
Count by 50 Percent
D
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), and Ceramic Flat (W) Packages,
Ceramic Chip Carriers (FK), and Standard
Plastic (N) and Ceramic (J) 300-mil DIPs
description
The ’HC393 contain eight flip-flops and additional
gating to implement two individual 4-bit counters
in a single package. The ’HC393 comprise two
independent 4-bit binary counters, each having a
clear (CLR) and a clock (CLK) input. N-bit binary
counters can be implemented with each package,
providing the capability of divide by 256. The
’HC393 have parallel outputs from each counter
stage so that any submultiple of the input count
frequency is available for system timing signals.
The SN54HC393 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74HC393 is characterized for
operation from –40°C to 85°C.
SN54HC393 ...J OR W PACKAGE
SN74HC393 . . . D, DB, OR N PACKAGE
SN54HC393 . . . FK PACKAGE
1Q
NC
1Q
NC
1Q
NC – No internal connection
(TOP VIEW)
1CLK
1CLR
1Q
A
1Q
B
1Q
C
1Q
D
GND
3212019
4
A
5
6
B
7
8
C
910111213
1
14
2
13
3
12
4
11
5
10
6
7
(TOP VIEW)
1CLR
1CLKNCV
D
NC
1Q
GND
9
8
CC
D2QC
V
CC
2CLK
2CLR
2Q
2Q
2Q
2Q
2CLK
18
17
16
15
14
2Q
A
B
C
D
2CLR
NC
2Q
A
NC
2Q
B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
SN54HC393, SN74HC393
COUNT
DUAL 4-BIT BINARY COUNTERS
SCLS143B – DECEMBER 1982 – REVISED MA Y 1997
logic symbol
FUNCTION TABLE COUNT SEQUENCE
0 L L L L
1 L LLH
2 L LHL
3 L LHH
4 L HLL
5 L HLH
6 L HHL
7 L HHH
8 H LLL
9 H LLH
10 H LHL
11 H LHH
12 H HLL
13 H HLH
14 H HHL
15 H H H H
(each counter)
OUTPUTS
Q
Q
D
C
Q
Q
B
A
†
CTRDIV16
1CLR
1CLK
2CLR
2CLK
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, N, and W packages.
2
1
12
13
CT=0
+
0
CT
3
11
10
3
1Q
A
4
1Q
B
5
1Q
C
6
1Q
D
2Q
A
2Q
B
9
2Q
C
8
2Q
D
2
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logic diagram, each counter (positive logic)
SN54HC393, SN74HC393
DUAL 4-BIT BINARY COUNTERS
SCLS143B – DECEMBER 1982 – REVISED MA Y 1997
CLR
CLK
absolute maximum ratings over operating free-air temperature range
R
Q
A
T
R
Q
B
T
R
Q
C
T
R
Q
D
T
†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
(VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 2): D package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DB package 158°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
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3
SN54HC393, SN74HC393
UNIT
†
PARAMETER
TEST CONDITIONS
V
UNIT
DUAL 4-BIT BINARY COUNTERS
SCLS143B – DECEMBER 1982 – REVISED MA Y 1997
recommended operating conditions
SN54HC393 SN74HC393
MIN NOM MAX MIN NOM MAX
V
V
V
V
V
t
t
T
†
If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced
grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally ,
the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
Supply voltage 2 5 6 2 5 6 V
CC
VCC = 2 V 1.5 1.5
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 V
I
Output voltage 0 V
O
Input transition (rise and fall) time
Operating free-air temperature –55 125 –40 85 °C
A
VCC = 4.5 V
VCC = 6 V 4.2 4.2
VCC = 2 V 0 0.5 0 0.5
VCC = 4.5 V
VCC = 6 V 0 1.8 0 1.8
VCC = 2 V 0 1000 0 1000
VCC = 4.5 V
VCC = 6 V 0 400 0 400
3.15 3.15
0 1.35 0 1.35
CC
CC
0 500 0 500
0 V
0 V
CC
CC
V
V
V
V
ns
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54HC393 SN74HC393
MIN TYP MAX MIN MAX MIN MAX
V
V
V
V
I
I
C
OH
OL
I
CC
CC
2 V 1.9 1.998 1.9 1.9
IOH = –20 µA
VI = VIH or V
VI = VIH or V
VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
VI = VCC or 0, IO = 0 6 V 8 160 80 µA
i
IL
IOH = –4 mA 4.5 V 3.98 4.3 3.7 3.84
IOH = –5.2 mA 6 V 5.48 5.8 5.2 5.34
IOL = 20 µA
IL
IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33
IOL = 5.2 mA 6 V 0.15 0.26 0.4 0.33
4.5 V 4.4 4.499 4.4 4.4
6 V 5.9 5.999 5.9 5.9
2 V 0.002 0.1 0.1 0.1
4.5 V 0.001 0.1 0.1 0.1
6 V 0.001 0.1 0.1 0.1
2 V to 6 V 3 10 10 10 pF
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
V
UNIT
twPulse duration
ns
PARAMETER
V
UNIT
tpdCLK
ns
SN54HC393, SN74HC393
DUAL 4-BIT BINARY COUNTERS
SCLS143B – DECEMBER 1982 – REVISED MA Y 1997
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
TA = 25°C SN54HC393 SN74HC393
CC
MIN MAX MIN MAX MIN MAX
2 V 0 6 0 4.2 0 5
f
clock
t
su
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
Clock frequency
Setup time, CLR inactive
f
max
t
PHL
t
t
CLK high or low
CLR high
FROM TO
(INPUT) (OUTPUT)
CLK Q
CLR Any
Q
Q
Q
Q
Any
A
A
B
C
D
4.5 V
6 V 0 36 0 25 0 28
2 V 80 120 100
4.5 V 16 24 20
6 V 14 20 18
2 V 80 120 100
4.5 V 16 24 20
6 V 14 20 18
2 V 25 25 25
4.5 V
6 V 5 5 5
CC
MIN TYP MAX MIN MAX MIN MAX
2 V 6 10 4.2 5
4.5 V 31 50 21 25
6 V 36 60 25 28
2 V 50 120 180 150
4.5 V 15 24 36 30
6 V 13 20 31 26
2 V 72 190 285 240
4.5 V 22 38 57 47
6 V 18 32 48 40
2 V 91 240 360 300
4.5 V 28 48 72 60
6 V 22 41 61 51
2 V 100 290 430 360
4.5 V 32 58 87 72
6 V 24 50 74 62
2 V 45 165 250 205
4.5 V 17 33 49 41
6 V 14 28 42 35
2 V 28 75 110 95
4.5 V 8 15 22 19
6 V 6 13 19 16
0 31 0 21 0 25
5 5 5
TA = 25°C SN54HC393 SN74HC393
MHz
ns
MHz
ns
ns
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
Power dissipation capacitance per counter No load 40 pF
pd
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5
SN54HC393, SN74HC393
DUAL 4-BIT BINARY COUNTERS
SCLS143B – DECEMBER 1982 – REVISED MA Y 1997
PARAMETER MEASUREMENT INFORMATION
50%
Test
Point
CL = 50 pF
(see Note A)
t
h
50%50%
From Output
Under Test
LOAD CIRCUIT
Reference
Input
t
su
Data
Input
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
90% 90%
t
r
VOLTAGE WAVEFORMS
V
0 V
V
0 V
CC
CC
V
CC
0 V
V
50%50%
OH
10%10%
V
OL
t
f
V
OH
90%90%
V
OL
t
r
High-Level
Pulse
Low-Level
Pulse
Input
V
CC
0 V
V
CC
10%10%
0 V
t
f
In-Phase
Output
Out-of-Phase
Output
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
t
t
PLH
PHL
50%
t
w
50%
VOLTAGE WAVEFORMS
PULSE DURATIONS
90% 90%
t
r
50% 50%
10% 10%
t
f
VOLTAGE WAVEFORMS
50%
t
50%
50%
t
PHL
PLH
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. For clock inputs, f
D. The outputs are measured one at a time with one input transition per measurement.
E. t
PLH
and t
PHL
is measured when the input duty cycle is 50%.
max
are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
6
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Copyright 1998, Texas Instruments Incorporated
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