Texas Instruments SN54HC259J, SN74HC259NSR, SN74HC259PWLE, SN74HC259PWR, SN74HC259D Datasheet
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SN54HC259, SN74HC259
8-BIT ADDRESSABLE LATCHES
SCLS134B – DECEMBER 1982 – REVISED MA Y 1997
D
8-Bit Parallel-Out Storage Register
Performs Serial-to-Parallel Conversion With
Storage
D
Asynchronous Parallel Clear
D
Active-High Decoder
D
Enable Input Simplifies Expansion
D
Expandable for n-Bit Applications
D
Four Distinct Functional Modes
D
Package Options Include Plastic
Small-Outline (D), Thin Shrink
Small-Outline (PW), and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs
description
These 8-bit addressable latches are designed for
general-purpose storage applications in digital
systems. Specific uses include working registers,
serial-holding registers, and active-high decoders
or demultiplexers. They are multifunctional
devices capable of storing single-line data in eight
addressable latches, and being a 1-of-8 decoder
or demultiplexer with active-high outputs.
Four distinct modes of operation are selectable by
controlling the clear (CLR
In the addressable-latch mode, data at the data-in
terminal is written into the addressed latch. The
addressed latch follows the data input with all
unaddressed latches remaining in their previous
states. In the memory mode, all latches remain in
their previous states and are unaffected by the
data or address inputs. T o eliminate the possibility
of entering erroneous data in the latches, G
should be held high (inactive) while the address
lines are changing. In the 1-of-8 decoding or
demultiplexing mode, the addressed output
follows the level of the D input with all other
outputs low. In the clear mode, all outputs are low
and unaffected by the address and data inputs.
) and enable (G) inputs.
SN54HC259 ...J OR W PACKAGE
SN74HC259 . . . D, N, OR PW PACKAGE
SN54HC259 . . . FK PACKAGE
S2
Q0
NC
Q1
Q2
NC – No internal connection
(TOP VIEW)
S0
1
S1
2
S2
3
Q0
4
Q1
5
Q2
6
Q3
7
GND
8
(TOP VIEW)
S1S0NC
3212019
4
5
6
7
8
910111213
Q3
GND
NC
16
15
14
13
12
11
10
9
CC
V
Q4
V
CC
CLR
G
D
Q7
Q6
Q5
Q4
CLR
18
17
16
15
14
Q5
G
D
NC
Q7
Q6
The SN54HC259 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74HC259 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
SN54HC259, SN74HC259
ADDRESSED
OTHER
FUNCTION
8-BIT ADDRESSABLE LATCHES
SCLS134B – DECEMBER 1982 – REVISED MA Y 1997
INPUTS
Function Tables
FUNCTION
OUTPUT OF
EACH
CLR G
H L D Q
H HQiOQ
L LD L 8-line demultiplexer
L H L L Clear
LATCH
LATCH SELECTION
SELECT INPUTS
S2 S1 S0
L L L 0
L LH 1
L HL 2
L HH 3
H LL 4
H LH 5
H HL 6
H H H 7
OUTPUT
iO
iO
ADDRESSED
Addressable latch
Memory
LATCH
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC259, SN74HC259
8-BIT ADDRESSABLE LATCHES
SCLS134B – DECEMBER 1982 – REVISED MA Y 1997
logic symbol
†
S0
S1
S2
CLR
1
2
3
14
G
13
D
15
0
2
G8
Z9
Z10
9, 0D
10, 0R
9, 1D
10, 1R
9, 2D
10, 2R
9, 3D
10, 3R
9, 4D
10, 4R
9, 5D
10, 5R
9, 6D
10, 6R
9, 7D
10, 7R
8M
0
7
4
Q0
5
Q1
6
Q2
7
Q3
9
Q4
10
Q5
11
Q6
12
Q7
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, N, PW, and W packages.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
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