SN54HC174, SN74HC174
HEX D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS119B – DECEMBER 1982 – REVISED MAY 1997
D
Contain Six Flip-Flops With Single-Rail
Outputs
D
Applications Include:
– Buffer/Storage Registers
– Shift Registers
– Pattern Generators
D
Package Options Include Plastic
Small-Outline (D) and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs
description
These monolithic positive-edge-triggered D-type
flip-flops have a direct clear (CLR) input.
Information at the data (D) inputs meeting the
setup time requirements is transferred to the
outputs on the positive-going edge of the clock
(CLK) pulse. Clock triggering occurs at a
particular voltage level and is not directly related
to the transition time of the positive-going edge of
CLK. When CLK is at either the high or low level,
the D input has no effect at the output.
SN54HC174 ...J OR W PACKAGE
SN74HC174 . . . D OR N PACKAGE
SN54HC174 . . . FK PACKAGE
1D
2D
NC
2Q
3D
(TOP VIEW)
CLR
1
1Q
2
1D
3
2D
4
2Q
5
3D
6
3Q
7
GND
8
(TOP VIEW)
1Q
3212019
4
5
6
7
8
910111213
CLR
NC
16
15
14
13
12
11
10
9
V
CC
V
CC
6Q
6D
5D
5Q
4D
4Q
CLK
6Q
18
17
16
15
14
6D
5D
NC
5Q
4D
The SN54HC174 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74HC174 is characterized for
operation from –40°C to 85°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
CLR CLK D
L X X L
H ↑ HH
H ↑ LL
H L X Q
OUTPUT
Q
0
NC
CLK
4Q
3Q
GND
NC – No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
SN54HC174, SN74HC174
HEX D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS119B – DECEMBER 1982 – REVISED MAY 1997
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, N, and W packages.
†
CLR
CLK
1D
2D
3D
4D
5D
6D
1
9
3
4
6
11
13
14
R
C1
1D
logic diagram (positive logic)
1
CLR
9
CLK
1D
3
1D
C1
R
10
12
15
2
1Q
5
2Q
7
3Q
4Q
5Q
6Q
2
1Q
To Five Other Channels
Pin numbers shown are for the D, J, N, and W packages.
absolute maximum ratings over operating free-air temperature range
‡
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
(VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 2): D package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
N package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
2
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UNIT
PARAMETER
TEST CONDITIONS
V
UNIT
recommended operating conditions
V
V
V
V
V
t
t
T
Supply voltage 2 5 6 2 5 6 V
CC
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 V
I
Output voltage 0 V
O
Input transition (rise and fall) time
Operating free-air temperature –55 125 –40 85 °C
A
SN54HC174, SN74HC174
HEX D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS119B – DECEMBER 1982 – REVISED MAY 1997
SN54HC174 SN74HC174
MIN NOM MAX MIN NOM MAX
VCC = 2 V 1.5 1.5
VCC = 4.5 V
VCC = 6 V 4.2 4.2
VCC = 2 V 0 0.5 0 0.5
VCC = 4.5 V
VCC = 6 V 0 1.8 0 1.8
VCC = 2 V 0 1000 0 1000
VCC = 4.5 V
VCC = 6 V 0 400 0 400
3.15 3.15
0 1.35 0 1.35
CC
CC
0 500 0 500
0 V
0 V
CC
CC
V
V
V
V
ns
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54HC174 SN74HC174
MIN TYP MAX MIN MAX MIN MAX
V
V
V
V
I
I
C
OH
OL
I
CC
i
CC
2 V 1.9 1.998 1.9 1.9
IOH = –20 µA
VI = VIH or V
VI = VIH or V
VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
VI = VCC or 0, IO = 0 6 V 8 160 80 µA
IL
IOH = –4 mA 4.5 V 3.98 4.3 3.7 3.84
IOH = –5.2 mA 6 V 5.48 5.8 5.2 5.34
IOL = 20 µA
IL
IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33
IOL = 5.2 mA 6 V 0.15 0.26 0.4 0.33
4.5 V 4.4 4.499 4.4 4.4
6 V 5.9 5.999 5.9 5.9
2 V 0.002 0.1 0.1 0.1
4.5 V 0.001 0.1 0.1 0.1
6 V 0.001 0.1 0.1 0.1
2 V to 6 V 3 10 10 10 pF
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54HC174, SN74HC174
V
UNIT
twPulse duration
ns
tsuSetup time before CLK↑
ns
↑
PARAMETER
V
UNIT
t
ns
HEX D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS119B – DECEMBER 1982 – REVISED MAY 1997
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
TA = 25°C SN54HC174 SN74HC174
CC
MIN MAX MIN MAX MIN MAX
2 V 0 6 0 4.2 0 5
f
clock
t
h
Clock frequency
p
Hold time, data after CLK
CLR low
CLK high or low
Data
CLR inactive
4.5 V
6 V 0 36 0 25 0 29
2 V 80 120 100
4.5 V 16 24 20
6 V 14 20 17
2 V 80 120 100
4.5 V 16 24 20
6 V 14 20 17
2 V 100 150 125
4.5 V 20 30 25
6 V 17 25 21
2 V 100 150 125
4.5 V 20 30 25
6 V 17 25 21
2 V 0 0 0
4.5 V 0 0 0
6 V 0 0 0
0 31 0 21 0 25
MHz
ns
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54HC174 SN74HC174
MIN TYP MAX MIN MAX MIN MAX
MHz
ns
f
max
pd
t
t
FROM TO
(INPUT) (OUTPUT)
CLR Any
CLK Any
Any
CC
2 V 6 9 4.2 5
4.5 V 31 44 21 25
6 V 36 50 25 29
2 V 58 160 240 200
4.5 V 17 32 48 40
6 V 14 27 41 34
2 V 58 160 240 200
4.5 V 17 32 48 40
6 V 14 27 41 34
2 V 38 75 110 90
4.5 V 8 15 22 19
6 V 6 13 19 16
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
Power dissipation capacitance per flip-flop No load 27 pF
pd
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50%
Test
Point
CL = 50 pF
(see Note A)
t
h
50%50%
From Output
Under Test
LOAD CIRCUIT
Reference
Input
t
su
Data
Input
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
90% 90%
t
r
VOLTAGE WAVEFORMS
SN54HC174, SN74HC174
HEX D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS119B – DECEMBER 1982 – REVISED MAY 1997
V
0 V
V
0 V
CC
CC
V
CC
0 V
V
50%50%
OH
10%10%
V
OL
t
f
V
OH
90%90%
V
OL
t
r
High-Level
Pulse
Low-Level
Pulse
Input
V
CC
0 V
V
CC
10%10%
0 V
t
f
In-Phase
Output
Out-of-Phase
Output
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
t
t
PLH
PHL
50%
t
w
50%
VOLTAGE WAVEFORMS
PULSE DURATIONS
90% 90%
t
r
50% 50%
10% 10%
t
f
VOLTAGE WAVEFORMS
50%
t
50%
50%
t
PHL
PLH
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. For clock inputs, f
D. The outputs are measured one at a time with one input transition per measurement.
E. t
PLH
and t
PHL
is measured when the input duty cycle is 50%.
max
are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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5
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