Texas Instruments SN54HC164J, SN74HC164N, SN74HC164N3, SN74HC164D, SN74HC164DR Datasheet
...
SN54HC164, SN74HC164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS115B – DECEMBER 1982 – REVISED MAY 1997
D
AND-Gated (Enable/Disable) Serial Inputs
D
Fully Buffered Clock and Serial Inputs
D
Direct Clear
D
Package Options Include Plastic
Small-Outline (D) and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs
description
These 8-bit shift registers feature AND-gated
serial inputs and an asynchronous clear (CLR)
input. The gated serial (A and B) inputs permit
complete control over incoming data; a low at
either input inhibits entry of the new data and
resets the first flip-flop to the low level at the next
clock (CLK) pulse. A high-level input enables the
other input, which then determines the state of the
first flip-flop. Data at the serial inputs can be
changed while CLK is high or low, provided the
minimum setup time requirements are met.
Clocking occurs on the low-to-high-level transition
of CLK.
The SN54HC164 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74HC164 is characterized for
operation from –40°C to 85°C.
SN54HC164 ...J OR W PACKAGE
SN74HC164 ...D OR N PACKAGE
SN54HC164 . . . FK PACKAGE
Q
A
NC
Q
B
NC
Q
C
NC – No internal connection
(TOP VIEW)
A
1
B
2
Q
3
A
Q
4
B
Q
5
C
Q
6
D
GND
7
(TOP VIEW)
BANC
3212019
4
5
6
7
8
910111213
D
Q
GND
NC
14
13
12
11
10
9
8
CC
V
CLK
V
Q
Q
Q
Q
CLR
CLK
H
Q
18
17
16
15
14
CLR
CC
H
G
F
E
Q
NC
Q
NC
Q
G
F
E
CLR CLK A B Q
L X X X L L L
H LXXQA0Q
H ↑ HHHQ
H ↑ LXLQ
H ↑ X L L Q
QA0, QB0, QH0 = the level of QA, QB, or QH, respectively,
before the indicated steady-state input conditions were
established
QAn, QGn = the level of QA or QG before the most recent
↑ transition of CLK: indicates a 1-bit shift
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
FUNCTION TABLE
INPUTS
OUTPUTS
A
QB...Q
B0QH0
AnQGn
AnQGn
AnQGn
H
Copyright 1997, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54HC164, SN74HC164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS115B – DECEMBER 1982 – REVISED MAY 1997
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, N, and W packages.
†
SRG8
R
C1/
&
1D
CLR
CLK
9
8
1
A
2
B
logic diagram (positive logic)
8
CLK
10
11
12
13
3
Q
A
4
Q
B
5
Q
C
6
Q
D
Q
E
Q
F
Q
G
Q
H
1
A
2
B
9
CLR
Pin numbers shown are for the D, J, N, and W packages.
1D
R
C1
C1
1D
R
3
Q
A
4
Q
B
1D
R
C1
C1
1D
R
5
Q
C
6
Q
C1
1D
R
10
D
Q
C1
1D
R
11
E
Q
C1
1D
R
12
F
Q
C1
1D
R
13
G
Q
H
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
typical clear, shift, and clear sequence
CLR
A
B
Serial InputsOutputs
CLK
Q
A
Q
B
Q
C
Q
D
Q
E
SN54HC164, SN74HC164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS115B – DECEMBER 1982 – REVISED MAY 1997
Q
F
Q
G
Q
H
Clear Clear
absolute maximum ratings over operating free-air temperature range
Supply voltage range, V
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
†
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 2): D package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
N package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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