SN54HC153, SN74HC153
DUAL 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS
SCLS112B – DECEMBER 1982 – REVISED MAY 1997
D
Permit Multiplexing from n Lines to One
Line
D
Perform Parallel-to-Serial Conversion
D
Strobe (Enable) Line Provided for
Cascading (N Lines to n Lines)
D
Package Options Include Plastic
Small-Outline (D), Thin Shrink
Small-Outline (PW), and Ceramic Flat
(W) Packages, Ceramic Chip Carriers
(FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
Each of these data selectors/multiplexers
contains inverters and drivers to supply full binary
decoding data selection to the AND-OR gates.
Separate strobe (G
of the two 4-line sections.
The SN54HC153 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74HC153 is characterized for
operation from –40°C to 85°C.
) inputs are provided for each
SN54HC153 ...J OR W PACKAGE
SN74HC153 . . . D, N, OR PW PACKAGE
SN54HC153 . . . FK PACKAGE
1C3
1C2
NC
1C1
1C0
(TOP VIEW)
1G
1
B
2
1C3
3
1C2
4
5
1C1
6
1C0
7
1Y
GND
8
(TOP VIEW)
B1GNC
3212019
4
5
6
7
8
910111213
16
15
14
13
12
11
10
9
CC
V
V
2G
A
2C3
2C2
2C1
2C0
2Y
2G
18
17
16
15
14
CC
A
2C3
NC
2C2
2C1
NC – No internal connection
FUNCTION TABLE
INPUTS
SELECT
B A C0 C1 C2 C3
X X X X X X H L
L LLXXXL L
L LHXXXL H
L HXLXXL L
L HXHXXL H
H LXXLXL L
H LXXHXL H
H HXXXLL L
H H X X X H L H
†
Select inputs A and B are common to both sections.
†
DATA
1Y
GND
NC
2Y
2C0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
SN54HC153, SN74HC153
DUAL 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS
SCLS112B – DECEMBER 1982 – REVISED MAY 1997
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, N, PW, and W packages.
†
1G
1C0
1C1
1C2
1C3
2G
2C0
2C1
2C2
2C3
14
A
2
B
1
6
5
4
3
15
10
11
12
13
0
1
EN
0
1
2
3
G
0
3
MUX
7
1Y
9
2Y
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
14
A
2
B
1
1G
6
1C0
5
1C1
4
1C2
3
1C3
SN54HC153, SN74HC153
DUAL 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS
SCLS112B – DECEMBER 1982 – REVISED MAY 1997
TG
TG
TG
7
1Y
TG
TG
TG
15
2G
10
2C0
11
2C1
12
2C2
13
2C3
Pin numbers shown are for the D, J, N, PW, and W packages.
TG
TG
TG
TG
TG
TG
9
2Y
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3