Texas Instruments SN54HC126J, SN74HC126D, SN74HC126DBLE, SN74HC126DBR, SN74HC126DR Datasheet
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SN54HC126, SN74HC126
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS103C – MARCH 1984 – REVISED FEBRUARY 1999
D
High-Current 3-State Outputs Interface
Directly With System Bus or Can Drive up
to 15 LSTTL Loads
D
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), and Ceramic Flat (W) Packages,
Ceramic Chip Carriers (FK), and Standard
Plastic (N) and Ceramic (J) DIPs
description
These quadruple bus buffer gates feature
independent line drivers with 3-state outputs.
Each output is disabled when the associated
output-enable (OE) input is low.
The SN54HC126 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74HC126 is characterized for
operation from –40°C to 85°C.
FUNCTION TABLE
(each buffer)
INPUTS
OE A
H H H
H LL
LXZ
OUTPUT
Y
SN54HC126 ...J OR W PACKAGE
SN74HC126 . . . D, DB, OR N PACKAGE
SN54HC126 . . . FK PACKAGE
1Y
NC
2OE
NC
2A
NC – No internal connection
(TOP VIEW)
1OE
1
1A
2
1Y
3
2OE
4
2A
5
6
2Y
GND
7
(TOP VIEW)
1A
3212019
4
5
6
7
8
910111213
2Y
1OE
GND
NC
NC
14
13
12
11
10
9
8
V
3Y
CC
V
CC
4OE
4A
4Y
3OE
3A
3Y
4OE
18
17
16
15
14
3A
4A
NC
4Y
NC
3OE
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, N, and W packages.
†
1
1OE
2
1A
4
2OE
5
2A
10
3OE
9
3A
13
4OE
12
4A
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EN
3
1Y
6
2Y
8
3Y
11
4Y
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
1
SN54HC126, SN74HC126
UNIT
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS103C – MARCH 1984 – REVISED FEBRUARY 1999
logic diagram (positive logic)
1
1OE
2
1A 1Y
4
2OE
5
2A 2Y
Pin numbers shown are for the D, DB, J, N, and W packages.
3
6
absolute maximum ratings over operating free-air temperature range
Supply voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
(VO = 0 to VCC) ±35 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
or GND ±70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 2): D package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
10
3OE
9
3A 3Y
13
4OE
12
4A 4Y
8
11
†
DB package 158°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 3)
SN54HC126 SN74HC126
MIN NOM MAX MIN NOM MAX
V
V
V
V
V
t
t
T
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 2 5 6 2 5 6 V
CC
VCC = 2 V 1.5 1.5
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 V
I
Output voltage 0 V
O
Input transition (rise and fall) time
Operating free-air temperature –55 125 –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
VCC = 4.5 V
VCC = 6 V 4.2 4.2
VCC = 2 V 0 0.5 0 0.5
VCC = 4.5 V 0 1.35 0 1.35
VCC = 6 V 0 1.8 0 1.8
VCC = 2 V 0 1000 0 1000
VCC = 4.5 V
VCC = 6 V 0 400 0 400
, literature number SCBA004.
3.15 3.15
CC
CC
0 500 0 500
0 V
0 V
CC
CC
V
V
V
V
ns
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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