Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
description
These quadruple bus transceivers are designed
for asynchronous communications between data
buses. The control function implementation allows
for maximum flexibility in timing. These devices
allow data transmission from the A bus to the
B bus or from the B bus to the A bus depending
upon the logic levels at the output-enable (OEBA
and OEAB
be used to disable the device so that the buses are
effectively isolated.
The dual-enable configuration gives the
quadruple bus transceivers the capability to store
data by simultaneous enabling of OEBA and
OEAB
transceiver configuration. Thus, when both control
inputs are enabled and all other data sources to
the two sets of bus lines are at high impedance,
both sets of bus lines (eight in all) remain at their
states. The 4-bit codes appearing on the two sets
of buses will be identical for the ′F243.
) inputs. The output-enable inputs can
. Each output reinforces its input in this
SN54F243 ...J PACKAGE
SN74F243 ...D OR N PACKAGE
OEAB
A1
NC
A2
NC
A3
NC – No internal connection
(TOP VIEW)
14
13
12
11
10
NC
NC
9
8
CC
V
B4
V
CC
OEBA
NC
B1
B2
B3
B4
OEBA
18
17
16
15
14
B3
1
NC
2
A1
3
A2
4
A3
5
A4
6
GND
SN54F243 . . . FK PACKAGE
7
(TOP VIEW)
NC
OEAB
3212019
4
5
6
7
8
910111213
A4
GND
NC
NC
B1
NC
B2
The SN54F243 is characterized for operation over
the full military temperature range of –55°C to
125°C. The SN74F243 is characterized for
operation from 0°C to 70°C.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
FUNCTION TABLE
INPUTS
OEAB
OEBA
LLA to B
HHB to A
HLIsolation
LH
Latch A and B
(A = B)
Copyright 1993, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2–1
SN54F243, SN74F243
QUADRUPLE BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SDFS086 – MARCH 1987 – REVISED OCTOBER 1993
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
†
OEBA
OEAB
A1
A2
A3
A4
13
1
3
4
5
6
EN1
EN2
1
2
logic diagram (positive logic)
A1
1
3
OEAB
13
11
11
10
9
8
B1
B2
B3
B4
OEBA
B1
4
A2
5
A3
6
A4
Pin numbers shown are for the D, J, and N packages.
10
B2
9
B3
8
B4
2–2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54F243, SN74F243
UNIT
QUADRUPLE BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SDFS086 – MARCH 1987 – REVISED OCTOBER 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input voltage ratings may be exceeded provided the input current ratings are observed.
t
¶
NOTE 3: Load circuits and waveforms are shown in Section 1.
PLZ
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
FROM
INPUT
TO
OUTPUT
RL = 500 Ω,
TA = 25°C
′F243SN54F243SN74F243
MINTYPMAXMINMAXMINMAX
1.73.65.21.26.51.26.2
1.73.65.21.28.51.26.5
1.23.95.71.281.26.7
1.25.47.51.210.51.28.5
1.24.1617.517
24.5628.527
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500Ω,
TA = MIN to MAX
¶
UNIT
2–4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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