TEXAS INSTRUMENTS SN54BCT374 Technical data

0°C to 70°C

SOIC

DW

BCT374

D

Operating Voltage Range of 4.5 V to 5.5 V

D

State-of-the-Art BiCMOS Design
Significantly Reduces I

D

Full Parallel Access for Loading

D

Buffered Control Inputs

CCZ

SN54BCT374, SN74BCT374

OCTAL EDGE-TRIGGERED D-TYPE LATCHES

WITH 3-STATE OUTPUTS

SCBS019C – SEPTEMBER 1988 – REVISED MARCH 2003

D

3-State Outputs Drive Bus Lines or Buffer
Memory Address Registers

D

ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)

SN54BCT374 ...J OR W PACKAGE

SN74BCT374 ... DW, N, OR NS PACKAGE

OE

1Q
1D
2D
2Q
3Q
3D
4D
4Q

GND

(TOP VIEW)

1

20

2

19

3

18

4

17

5

16

6

15

7

14

8

13

9

12

10

11

V

CC

8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK

SN54BCT374 ...FK PACKAGE

2D
2Q
3Q
3D
4D

(TOP VIEW)

1D1QOE

3 2 1 20 19

4
5
6
7
8

910111213

4Q

CLK

GND

V

5Q

CC

8Q

18
17
16
15
14

5D

8D
7D
7Q
6Q
6D

description/ordering information

These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.

The eight flip-flops of the ’BCT374 devices are edge-triggered D-type flip-flops. On the positive transition of the
clock (CLK) input, the Q outputs are set to the logic levels that were set up at the data (D) inputs.

A buffered output-enable (OE
or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly . The high-impedance state and the increased drive provide the capability to drive bus lines without
need for interface or pullup components. The output-enable (OE
the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance
state.

) input can be used to place the eight outputs in either a normal logic state (high

) input does not affect internal operations of

T

A

PDIP – N Tube SN74BCT374N SN74BCT374N

–

SOP – NS T ape and reel SN74BCT374NSR BCT374
CDIP – J Tube SNJ54BCT374J SNJ54BCT374J

–55°C to 125°C

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

CFP – W Tube SNJ54BCT374W SNJ54BCT374W
LCCC – FK Tube SNJ54BCT374FK SNJ54BCT374FK

ORDERING INFORMATION

PACKAGE

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

†

Tube SN74BCT374DW
Tape and reel SN74BCT374DWR

ORDERABLE

PART NUMBER

TOP-SIDE
MARKING

Copyright  2003, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.

1

SN54BCT374, SN74BCT374
OCTAL EDGE-TRIGGERED D-TYPE LATCHES
WITH 3-STATE OUTPUTS

SCBS019C – SEPTEMBER 1988 – REVISED MARCH 2003

description/ordering information (continued)

T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

FUNCTION TABLE

(each flip-flop)

logic diagram (positive logic)

OE

CLK

1D

INPUTS

OE CLK D

L ↑ H H
L ↑ LL
L H or L X Q

H X X Z

1

11

3

1D

C1

OUTPUT

Q

0

2

1Q

To Seven Other Channels

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Input voltage range, V
Voltage range applied to any output in the disabled or power-off state, V
Voltage range applied to any output in the high state, V
Input clamp current, I

Current into any output in the low state: SN54BCT374 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

–0.5 V to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

O

–0.5 V to 5.5 V. . . . . . . . . . . . . . . .

O

SN74BCT374 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 2): DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

†

CC

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UNIT

PARAMETER

TEST CONDITIONS

UNIT

V

V

4.5 V

V

SN54BCT374, SN74BCT374

OCTAL EDGE-TRIGGERED D-TYPE LATCHES

WITH 3-STATE OUTPUTS

SCBS019C – SEPTEMBER 1988 – REVISED MARCH 2003

recommended operating conditions (see Note 3)

SN54BCT374 SN74BCT374

MIN NOM MAX MIN NOM MAX

V

CC

V

IH

V

IL

I

IK

I

OH

I

OL

T

A

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

†

All typical values are at VCC = 5 V, TA = 25°C.

‡

Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

Supply voltage 4.5 5 5.5 4.5 5 5.5 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input clamp current –18 –18 mA
High-level output current –2 –15 mA
Low-level output current 48 64 mA
Operating free-air temperature –55 125 0 70 °C

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

SN54BCT374 SN74BCT374

MIN TYP†MAX MIN TYP†MAX

V

IK

V

OH

OL

I

I

I

IH

I

IL

I

OS

I

OZH

I

OZL

I

CCL

I

CCH

I

CCZ

C

i

C

o

‡

VCC = 4.5 V, II = –18 mA –1.2 –1.2 V

IOH = –3 mA 2.4 3.3 2.4 3.3

VCC = 4.5 V

=

CC

VCC = 5.5 V, VI = 5.5 V 0.4 0.4 mA
VCC = 5.5 V, VI = 2.7 V 20 20 µA
VCC = 5.5 V, VI = 0.5 V –0.6 –0.6 mA
VCC = 5.5 V, VO = 0 –100 –225 –100 –225 mA
VCC = 5.5 V, VO = 2.7 V 50 50 µA
VCC = 5.5 V, VO = 0.5 V –50 –50 µA
VCC = 5.5 V 37 60 37 60 mA
VCC = 5.5 V 2 5 2 5 mA
VCC = 5.5 V 5 8 5 8 mA
VCC = 5 V, VI = 2.5 V or 0.5 V 6 6 pF
VCC = 5 V, VO = 2.5 V or 0.5 V 10 10 pF

IOH = –12 mA 2 3.2
IOH = –15 mA 2 3.1
IOL = 48 mA 0.38 0.55
IOL = 64 mA 0.42 0.55

V

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

SN54BCT374, SN74BCT374

CLK

Q

ns

OE

Q

ns

OE

Q

ns

OCTAL EDGE-TRIGGERED D-TYPE LATCHES
WITH 3-STATE OUTPUTS

SCBS019C – SEPTEMBER 1988 – REVISED MARCH 2003

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)

VCC = 5 V,

TA = 25°C
MIN MAX MIN MAX MIN MAX

f

clock

t

w

t

su

t

h

Clock frequency 70 70 70 MHz
Pulse duration CLK high 7 8 7 ns
Setup time before CLK↑
Hold time after CLK↑ Data high or low 0 0 0 ns

Data high or low 6.5 6.5 6.5 ns

switching characteristics (see Figure 1)

VCC = 5 V,
CL = 50 pF,

PARAMETER

f

max

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

†

PLZ

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

FROM

(INPUT)

TO

(OUTPUT)

R1 = 500 Ω,
R2 = 500 Ω,
TA = 25°C

’BCT374 SN54BCT374 SN74BCT374

MIN TYP MAX MIN MAX MIN MAX

70 70 70 MHz

2 7.2 9.1 2 11.6 2 10.6
2 7.1 8.8 2 10.6 2 10
1 8.3 10.1 1 12.7 1 12.3
1 8.6 10.6 1 13 1 12.7
1 4.7 6.3 1 7.1 1 6.8
1 4.8 6.3 1 7.5 1 6.8

SN54BCT374 SN74BCT374

VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = 500 Ω,
R2 = 500 Ω,
TA = MIN to MAX

†

UNIT

UNIT

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54BCT374, SN74BCT374

OCTAL EDGE-TRIGGERED D-TYPE LATCHES

WITH 3-STATE OUTPUTS

SCBS019C – SEPTEMBER 1988 – REVISED MARCH 2003

PARAMETER MEASUREMENT INFORMATION

7 V (t

S1

From Output

Under Test

C

(see Note A)

3-STATE AND OPEN-COLLECTOR OUTPUTS

Timing Input

(see Note B)

Data Input

(see Note B)

L

LOAD CIRCUIT FOR

t

su

1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

, t

PZL

Open
(all others)

R1

1.5 V

, O.C.)

PLZ

Test
Point

R2

RL = R1 = R2

t

h

1.5 V

3 V

0 V

3 V

0 V

From Output

Under Test

(see Note A)

High-Level

Pulse

(see Note B)

Low-Level

Pulse

C

L

LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS

1.5 V

t

w

1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

R1

Test
Point

3 V

1.5 V
0 V

3 V

1.5 V
0 V

Input

(see Note B)

t

In-Phase

(see Note D)

Out-of-Phase

(see Note D)

NOTES: A. CL includes probe and jig capacitance.

PLH

Output

t

PHL

Output

PROPAGATION DELAY TIMES (see Note D)

B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, tr = tf≤ 2.5 ns, duty cycle = 50%.
C. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
E. When measuring propagation delay times of 3-state outputs, switch S1 is open.
F. All parameters and waveforms are not applicable to all devices.

1.5 V 1.5 V

1.5 V 1.5 V

VOLTAGE WAVEFORMS

Figure 1. Load Circuit and Voltage Waveforms

1.5 V1.5 V

t

t

PHL

PLH

3 V

0 V

V

V

V

V

OH

(see Notes C and D)

OL

OH

(see Notes C and D)

OL

Output

Control

(low-level enable)

Waveform 1

Waveform 2

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

t

PZL

1.5 V

t

PZH

1.5 V

VOLTAGE WAVEFORMS

t

PHZ

3 V

1.5 V1.5 V
0 V

t

PLZ

3.5 V

V

OL

0.3 V

V

OH

0.3 V
0 V

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5