Texas Instruments SN54AS885JT, SN74AS885DW, SN74AS885DWR, SN74AS885NT, SN74AS885NT3 Datasheet
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SN54AS885, SN74AS885
8-BIT MAGNITUDE COMPARATORS
SDAS236A – DECEMBER 1982 – REVISED JANUARY 1995
• Latchable P-Input Ports With Power-Up
Clear
SN54AS885 . . . JT PACKAGE
SN74AS885 . . . DW OR NT PACKAGE
(TOP VIEW)
• Choice of Logical or Arithmetic
(T wo’s Complement) Comparison
• Data and PLE Inputs Utilize pnp Input
Transistors to Reduce dc Loading Effects
• Approximately 35% Improvement in
ac Performance Over Schottky TTL While
Performing More Functions
• Cascadable to n Bits While Maintaining
High Performance
• 10% Less Power Than STTL for an 8-Bit
Comparison
• Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic
(NT) and Ceramic (JT) 300-mil DIPs
description
These advanced Schottky devices are capable of
performing high-speed arithmetic or logic
comparisons on two 8-bit binary or two’s
complement words. Two fully decoded decisions
about words P and Q are externally available at
two outputs. These devices are fully expandable
to any number of bits without external gates. To
compare words of longer lengths, the P > QOUT
and P < QOUT outputs of a stage handling less
significant bits can be connected to the P > QIN
and P < QIN inputs of the next stage handling
more significant bits. The cascading paths are
implemented with only a two-gate-level delay to
reduce overall comparison times for long words.
Two alternative methods of cascading are shown
in
application information
.
The latch is transparent when P latch-enable
(PLE) input is high; the P-input port is latched
when PLE is low. This provides the designer with temporary storage for the P-data word. The enable circuitry
is implemented with minimal delay times to enhance performance when cascaded for longer words. The PLE,
P, and Q data inputs utilize pnp input transistors to reduce the low-level current input requirement to typically
–0.25 mA, which minimizes dc loading effects.
L/A
1
24
P < QIN
P > QIN
SN54AS885 . . . FK PACKAGE
Q7
Q6
Q5
NC
Q4
Q3
Q2
NC – No internal connection
2
23
3
22
Q7
4
21
Q6
5
20
Q5
6
19
Q4
7
18
Q3
8
17
Q2
9
16
Q1
10
15
Q0
11
14
GND
12
13
(TOP VIEW)
P > QIN
P < QIN
L/A
NC
V
3212827
426
5
6
7
8
9
10
11
12 13
14 15 16 17 18
Q1
Q0
NC
GND
P > QOUT
V
CC
PLE
P7
P6
P5
P4
P3
P2
P1
P0
P < QOUT
P > QOUT
CC
PLE
P7
25
24
23
22
21
20
19
P0
P < QOUT
P6
P5
P4
NC
P3
P2
P1
The SN54AS885 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74AS885 is characterized for operation from 0°C to 70°C.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1995, Texas Instruments Incorporated
1
SN54AS885, SN74AS885
8-BIT MAGNITUDE COMPARATORS
SDAS236A – DECEMBER 1982 – REVISED JANUAR Y 1995
COMPARISON
Logical H P > Q X X H L
Logical H P < Q X XL H
†
Logical
Arithmetic L P AG Q X XH L
Arithmetic L Q AG P X XL H
Arithmetic
†
In these cases, P > QOUT follows P > QIN and P < QOUT follows P < QIN.
AG = arithmetically greater than
L/A
H P = Q H or L H or L H or L H or L
†
L P = Q H or L H or L H or L H or L
FUNCTION TABLE
INPUTS OUTPUTS
DATA
P0–P7,
Q0–Q7
P > QIN P < QIN P > QOUT P < QOUT
logic symbol
‡
L/A
PLE
P0
P1
P2
P3
P4
P5
P6
P7
P > QIN
P < QIN
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
1
23
15
16
17
18
19
20
21
22
3
2
11
10
9
8
7
6
5
4
M [LOGIC]
M [ARITH, 2s COMP]
C1
1D
>
<
0
7
Q
COMP
1=0 0
P
13
P > Q
7
P < Q
14
P > QOUT
P < QOUT
‡
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DW, JT, and NT packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
SN54AS885, SN74AS885
8-BIT MAGNITUDE COMPARATORS
SDAS236A – DECEMBER 1982 – REVISED JANUARY 1995
PLE
P7
P6
P5
P4
P3
P2
P1
P0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
P > QIN
P < QIN
L/A
23
22
21
20
19
18
17
16
15
4
5
6
7
8
9
10
11
1
C1
3
2
1D
Q7
Q7
Q6
Q6
Q5
Q5
Q4
Q4
Q3
Q3
Q2
Q2
Q1
Q1
Q0
P7
P7
P6
P6
P5
P5
P4
P4
P3
P3
P2
P2
P1
P1
P0
P0
Q0
ARITH
LOGIC
P2 = Q2
P1 = Q1
P0 = Q0
P7 = Q7
P6 = Q6
P5 = Q5
P3 = Q3
14
P < QOUT
13
P > QOUT
4MSB =
Pin numbers shown are for the DW, JT, and NT packages.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
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