Texas Instruments SN54AS756J, SN74AS756DW, SN74AS756DWR, SN74AS756N, SN74AS757DW Datasheet
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SN54AS756, SN74AS756, SN74AS757
OCTAL BUFFERS AND LINE DRIVERS
WITH OPEN-COLLECTOR OUTPUTS
SDAS040B – DECEMBER 1983 – REVISED JANUARY 1995
• Open-Collector Outputs Drive Bus Lines or
Buffer Memory Address Registers
• Eliminate the Need for 3-State Overlap
Protection
• pnp Inputs Reduce dc Loading
• Open-Collector Versions of ′AS240A and
′AS241
• Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic (N)
and Ceramic (J) 300-mil DIPs
description
These octal buffers and line drivers are designed
specifically to improve the performance and
density of 3-state memory address drivers, clock
drivers, and bus-oriented receivers and
transmitters by eliminating the need for 3-state
overlap protection. The designer has a choice of
selected combinations of inverting and
noninverting outputs, symmetrical active-low
output-enable (OE
OE and OE
fan-out and improved fan-in.
The SN54AS756 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74AS756 and SN74AS757 are
characterized for operation from 0°C to 70°C.
) inputs, and complementary
inputs. These devices feature high
SN74AS756, SN74AS757 . . . DW OR N PACKAGE
SN54AS756 ...J PACKAGE
(TOP VIEW)
1OE
1
1A1
2
2Y4
3
1A2
4
2Y3
5
1A3
6
2Y2
7
1A4
8
9
2Y1
GND
SN54AS756 . . . FK PACKAGE
1A2
2Y3
1A3
2Y2
1A4
†
2OE for ′AS756 or 2OE for SN74AS757
10
(TOP VIEW)
2Y4
1A1
3 2 1 20 19
4
5
6
7
8
910111213
2Y1
GND
20
19
18
17
16
15
14
13
12
11
V
1OE
2A1
V
2OE/2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
CC
18
17
16
15
14
1Y4
2A2 2OE
CC
1Y1
2A4
1Y2
2A3
1Y3
†
logic symbols
1
1OE
2
1A1
4
1A2
6
1A3
8
1A4
19
2OE
11
2A1
13
2A2
15
2A3
17
2A4
‡
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
‡
′AS756
EN
EN
18
16
14
12
1Y1
1Y2
1Y3
1Y4
9
2Y1
7
2Y2
5
2Y3
3
2Y4
1OE
1A1
1A2
1A3
1A4
2OE
2A1
2A2
2A3
2A4
1
2
4
6
8
19
11
13
15
17
SN74AS757
EN
18
1Y1
16
1Y2
14
1Y3
12
1Y4
EN
9
2Y1
7
2Y2
5
2Y3
3
2Y4
Copyright 1995, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54AS756, SN74AS756, SN74AS757
OCTAL BUFFERS AND LINE DRIVERS
WITH OPEN-COLLECTOR OUTPUTS
SDAS040B – DECEMBER 1983 – REVISED JANUARY 1995
logic diagrams (positive logic)
′AS756 SN74AS757
1
1OE
1OE
1
1A1
1A2
1A3
1A4
2OE
2A1
2A2
2A3
2A4
2
4
6
8
19
11
13
15
17
18
16
14
12
1Y1
1Y2
1Y3
1Y4
2OE
9
2Y1
7
2Y2
5
2Y3
3
2Y4
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
2
4
6
8
19
11
13
15
17
18
16
14
12
1Y1
1Y2
1Y3
1Y4
9
2Y1
7
2Y2
5
2Y3
3
2Y4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
Input voltage, V
Off-state output voltage 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
: SN54AS756 –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A
SN74AS756, SN74AS757 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . .
†
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AS756, SN74AS756, SN74AS757
VOLV
V
V
IL
CC,I
′AS756
V
5.5 V
I
mA
SN74AS757
V
5.5 V
OCTAL BUFFERS AND LINE DRIVERS
WITH OPEN-COLLECTOR OUTPUTS
SDAS040B – DECEMBER 1983 – REVISED JANUARY 1995
recommended operating conditions
SN54AS756
MIN NOM MAX MIN NOM MAX
V
V
V
V
I
T
CC
IH
IL
OH
OL
A
Supply voltage 4.5 5 5.5 4.5 5 5.5 V
High-level input voltage 2 2 V
Low-level input voltage 0.7 0.8 V
High-level output voltage 5.5 5.5 V
Low-level output current 48 64 mA
Operating free-air temperature –55 125 0 70 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS
V
IK
I
OH
I
I
I
IH
A inputs of
I
CC
†
All typical values are at VCC = 5 V, TA = 25°C.
SN74AS757 only
All other inputs
′
VCC = 4.5 V, II = –18 mA –1.2 –1.2 V
VCC = 4.5 V, VOH = 5.5 V 0.1 0.1 mA
= 4.5
CC
VCC = 5.5 V, VI = 7 V 0.1 0.1 mA
VCC = 5.5 V, VI = 2.7 V 20 20 µA
V
= 5.5 V, V
=
CC
=
CC
IOL = 48 mA 0.55
IOL = 64 mA 0.55
= 0.4 V
Outputs high 9 15 9 15
Outputs low 51 80 51 80
Outputs high 21 33 21 33
Outputs low 61 95 61 95
SN54AS756
MIN TYP†MAX MIN TYP†MAX
–1 –1
–0.5 –0.5
SN74AS756
SN74AS757
SN74AS756
SN74AS757
UNIT
UNIT
mA
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54AS756, SN74AS756, SN74AS757
(
)
(
)
(INPUT)
(OUTPUT)
A
Y
ns
OE
Y
ns
(
)
(
)
(INPUT)
(OUTPUT)
A
Y
ns
1OE
1Y
ns
2OE
2Y
ns
OCTAL BUFFERS AND LINE DRIVERS
WITH OPEN-COLLECTOR OUTPUTS
SDAS040B – DECEMBER 1983 – REVISED JANUARY 1995
switching characteristics (see Figure 1)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
PARAMETER
t
PLH
t
PHL
t
PLH
t
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
PHL
FROM
INPUT
TO
OUTPUT
switching characteristics (see Figure 1)
PARAMETER
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
PHL
FROM
INPUT
TO
OUTPUT
RL = 500 Ω
TA = MIN to MAX
SN54AS756 SN74AS756
MIN MAX MIN MAX
3 20 3 19
1 7 1 6
3 22 3 19.5
1 8.5 1 7.5
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500 Ω
TA = MIN to MAX
,
†
,
SN74AS757
MIN MAX
3 18.5
1 6
3 20
1 7
3 21
1 7.5
UNIT
†
UNIT
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
(see Note A)
SN54AS756, SN74AS756, SN74AS757
OCTAL BUFFERS AND LINE DRIVERS
WITH OPEN-COLLECTOR OUTPUTS
SDAS040B – DECEMBER 1983 – REVISED JANUARY 1995
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7 V
V
CC
S1
R
L
Test
Point
C
L
R
L
From Output
Under Test
(see Note A)
Test
Point
C
L
From Output
Under Test
(see Note A)
R1
C
L
RL = R1 = R2
Test
Point
R2
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
Timing
Input
t
su
Data
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
t
PZL
t
PZH
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
1.3 V
t
PHZ
1.3 V
1.3 V
t
1.3 V1.3 V
1.3 V1.3 V
FOR OPEN-COLLECTOR OUTPUTS
h
t
PLZ
LOAD CIRCUIT
3.5 V
0.3 V
3.5 V
0.3 V
3.5 V
0.3 V
[
3.5 V
V
OL
0.3 V
V
OH
0.3 V
[
0 V
High-Level
Low-Level
Out-of-Phase
(see Note C)
Pulse
Pulse
Input
In-Phase
Output
Output
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
1.3 V 1.3 V
t
w
1.3 V 1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.3 V 1.3 V
t
PLH
t
PHL
1.3 V 1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.3 V1.3 V
t
PHL
t
PLH
3.5 V
0.3 V
3.5 V
0.3 V
3.5 V
0.3 V
V
V
V
V
OH
OL
OH
OL
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
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5
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Copyright 1998, Texas Instruments Incorporated
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