Texas Instruments SN54AS374J, SN74AS374DW, SN74AS374DWR, SN74AS374N, SNJ54ALS374AFK Datasheet
...
SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999
D
D-Type Flip-Flops in a Single Package With
3-State Bus Driving True Outputs
D
Full Parallel Access for Loading
D
Buffered Control Inputs
D
Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic (N)
and Ceramic (J) DIPs
description
These octal D-type edge-triggered flip-flops
feature 3-state outputs designed specifically for
driving highly capacitive or relatively
low-impedance loads. They are particularly
suitable for implementing buffer registers, I/O
ports, bidirectional bus drivers, and working
registers.
On the positive transition of the clock (CLK) input,
the Q outputs are set to the logic levels set up at
the data (D) inputs.
A buffered output-enable (OE
eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In
the high-impedance state, the outputs neither
load nor drive the bus lines significantly. The
high-impedance state and the increased drive
provide the capability to drive bus lines without
interface or pullup components.
) input places the
SN54ALS374A, SN54AS374 . . . J PACKAGE
SN74ALS374A, SN74AS374 . . . DW OR N PACKAGE
SN54ALS374A, SN54AS374 . . . FK PACKAGE
2D
2Q
3Q
3D
4D
(TOP VIEW)
OE
1
1Q
2
1D
3
2D
4
2Q
5
3Q
6
3D
7
4D
8
9
4Q
GND
10
(TOP VIEW)
1D1QOE
3212019
4
5
6
7
8
910111213
4Q
GND
20
19
18
17
16
15
14
13
12
11
CLK
CC
V
5Q
V
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
18
17
16
15
14
5D 8Q
CC
8D
7D
7Q
6Q
6D
OE
does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The SN54ALS374A and SN54AS374 are characterized for operation over the full military temperature range
of –55°C to 125°C. The SN74ALS374A and SN74AS374 are characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(each flip-flop)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
INPUTS
OE CLK D
L ↑ H H
L ↑ LL
L H or L X Q
H X X Z
OUTPUT
Q
0
Copyright 1999, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374
UNIT
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999
logic symbol
1
OE
11
CLK
3
1D
4
2D
7
3D
8
4D
13
5D
14
6D
17
7D
18
8D
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
†
EN
C1
12
15
16
19
2
1Q
5
2Q
6
3Q
9
4Q
5Q
6Q
7Q
8Q
1D
logic diagram (positive logic)
1
OE
11
CLK
C1
1D
1D
3
To Seven Other Channels
2
1Q
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
Voltage applied to a disabled 3-state output –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 1): DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
‡
recommended operating conditions
V
V
V
I
I
T
OH
OL
Supply voltage 4.5 5 5.5 4.5 5 5.5 V
CC
High-level input voltage 2 2 V
IH
Low-level input voltage 0.7 0.8 V
IL
High-level output current –1 –2.6 mA
Low-level output current 12 24 mA
Operating free-air temperature –55 125 0 70 °C
A
SN54ALS374A SN74ALS374A
MIN NOM MAX MIN NOM MAX
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER
TEST CONDITIONS
UNIT
V
V
V
V
V
V
UNIT
PARAMETER
UNIT
CLK
Q
ns
OE
Q
ns
OE
Q
ns
SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ALS374A SN74ALS374A
MIN TYP†MAX MIN TYP†MAX
V
IK
V
OH
OL
I
OZH
I
OZL
I
I
I
IH
I
IL
‡
I
O
I
CC
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
VCC = 4.5 V, II = –18 mA –1.5 –1.5 V
VCC = 4.5 V to 5.5 V, IOH = –0.4 mA VCC–2 VCC–2
= 4.5
CC
= 4.5
CC
VCC = 5.5 V, VO = 2.7 V 20 20 µA
VCC = 5.5 V, VO = 0.4 V –20 –20 µA
VCC = 5.5 V, VI = 7 V 0.1 0.1 mA
VCC = 5.5 V, VI = 2.7 V 20 20 µA
VCC = 5.5 V, VI = 0.4 V –0.2 –0.2 mA
VCC = 5.5 V, VO = 2.25 V –20 –112 –30 –112 mA
VCC = 5.5 V
IOH = –1 mA 2.4 3.3
IOH = –2.6 mA 2.4 3.2
IOL = 12 mA 0.25 0.4 0.25 0.4
IOL = 24 mA 0.35 0.5
Outputs high 11 20 11 19
Outputs low 19 28 19 28
Outputs disabled 20 31 20 31
V
mA
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
SN54ALS374A SN74ALS374A
MIN MAX MIN MAX
f
clock
t
w
t
su
t
h
Clock frequency 30 35 MHz
Pulse duration CLK high or low 16.5 14 ns
Setup time Data before CLK↑ 10 10 ns
Hold time Data after CLK↑ 4 0 ns
switching characteristics over recommended operating conditions (unless otherwise noted
(see Figure 3)
SN54ALS374A SN74ALS374A
MIN MAX MIN MAX
30 35 MHz
3 14 3 12
5 17 5 16
3 18 3 17
5 21 5 18
1 11 1 10
2 19 2 18
f
max
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
FROM TO
(INPUT) (OUTPUT)
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374
UNIT
PARAMETER
TEST CONDITIONS
UNIT
V
4.5 V
VOLV
V
V
I
V
5.5 V
V
0.4 V
mA
UNIT
twPulse duration
ns
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999
recommended operating conditions
SN54AS374 SN74AS374
MIN NOM MAX MIN NOM MAX
V
V
V
I
OH
I
OL
T
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
V
V
I
OZH
I
OZL
I
I
I
IH
IL
I
O
I
CC
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
Supply voltage 4.5 5 5.5 4.5 5 5.5 V
CC
High-level input voltage 2 2 V
IH
Low-level input voltage 0.7 0.8 V
IL
High-level output current –12 –15 mA
Low-level output current 32 48 mA
Operating free-air temperature –55 125 0 70 °C
A
SN54AS374 SN74AS374
MIN TYP†MAX MIN TYP†MAX
IK
OH
OE, CLK
Data
‡
VCC = 4.5 V, II = –18 mA –1.2 –1.2 V
VCC = 4.5 V to 5.5 V, IOH = –2 mA VCC–2 VCC–2
=
CC
= 4.5
CC
VCC = 5.5 V, VO = 2.7 V 50 50 µA
VCC = 5.5 V, VO = 0.4 V –50 –50 µA
VCC = 5.5 V, VI = 7 V 0.1 0.1 mA
VCC = 5.5 V, VI = 2.7 V 20 20 µA
,
=
CC
VCC = 5.5 V, VO = 2.25 V –30 –112 –30 –112 mA
VCC = 5.5 V
IOH = –12 mA 2.4 3.2
IOH = –15 mA 2.4 3.3
IOL = 32 mA 0.29 0.5
IOL = 48 mA 0.34 0.5
=
I
Outputs high 77 120 77 120
Outputs low 84 128 84 128
Outputs disabled 84 128 84 128
–0.5 –0.5
–3 –2
V
mA
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
SN54AS374 SN74AS374
MIN MAX MIN MAX
f
clock
t
su
t
h
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
4
Clock frequency 100* 125 MHz
CLK high 5.5* 4
CLK low 3* 3
Setup time Data before CLK↑ 3* 2 ns
Hold time Data after CLK↑ 3* 2 ns
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER
UNIT
CLK
Q
ns
OE
Q
ns
OE
Q
ns
SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999
switching characteristics over recommended operating conditions (unless otherwise noted)
(see Figure 3)
FROM TO
(INPUT) (OUTPUT)
f
max
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
SN54AS374 SN74AS374
MIN MAX MIN MAX
100* 125 MHz
3 11 3 8
4 11.5 4 9
2 7 2 6
3 11 3 10
2 10 2 6
2 7 2 6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999
APPLICATION INFORMATION
’ALS139
Four SN54ALS374A,
SN74ALS374A,
or ’AS374
EN
C
8 8
Output-Enable
Select
Input Clock
Select
Clock
A
B
G
A
B
G
X/Y
1
2
EN
0
1
2
3
8 8
Input Output
EN
C
8 8
EN
C
8 8
EN
C
8 8
Figure 1. Expandable 4-Word by 8-Bit General File Register
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Output Enable 1
Clock 1
SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999
APPLICATION INFORMATION
SN54ALS374A,
SN74ALS374A,
or ’AS374
EN
C1
1D
Bidirectional
Data Bus 1
Output Enable 2
Clock 2
Clock 1
Bus-Exchange
Clock
Clock 2
Bidirectional
Data Bus 2
SN54ALS374A,
SN74ALS374A,
or ’AS374
EN
C1
1D
H
H
Clock Circuit for Bus Exchange
Figure 2. Bidirectional Bus Driver
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
V
CC
7 V
S1
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT FOR
BI-STATE TOTEM-POLE OUTPUTS
Timing
Input
t
su
Data
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
t
PZL
Waveform 1
S1 Closed
(see Note B)
t
PZH
Waveform 2
S1 Open
(see Note B)
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
VOLTAGE WAVEFORMS
Test
Point
500 Ω
1.3 V
t
h
1.3 V1.3 V
1.3 V 1.3 V
1.3 V
1.3 V
VOL + 0.3 V
500 Ω
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT FOR
OPEN-COLLECTOR OUTPUTS
3.5 V
0.3 V
3.5 V
0.3 V
3.5 V
0.3 V
t
PLZ
≈3.5 V
V
OL
t
PHZ
V
VOH – 0.3 V
OH
≈0 V
Out-of-Phase
Test
Point
High-Level
Pulse
Low-Level
Pulse
Input
In-Phase
Output
Output
(see Note C)
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT FOR
3-STATE OUTPUTS
1.3 V 1.3 V
t
w
1.3 V 1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.3 V 1.3 V
t
PLH
1.3 V 1.3 V
t
PHL
1.3 V 1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
500 Ω
500 Ω
3.5 V
0.3 V
3.5 V
0.3 V
t
PHL
t
PLH
Test
Point
3.5 V
0.3 V
V
OH
V
OL
V
OH
V
OL
Figure 3. Load Circuits and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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Copyright 1999, Texas Instruments Incorporated
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