Texas Instruments SN54AS194J, SN74AS194D, SN74AS194DR, SN74AS194N, SNJ54AS194FK Datasheet

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SN54AS194, SN74AS194

4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS

SDAS212A – DECEMBER 1983 – REVISED DECEMBER 1994

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

• Parallel-to-Serial, Serial-to-Parallel

Conversions

• Left or Right Shifts

• Parallel Synchronous Loading

• Direct Overriding Clear

• Temporary Data-Latching Capability

• Package Options Include Plastic

Small-Outline Packages (D), Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

description

These 4-bit bidirectional universal shift registers feature parallel outputs, right-shift and left-shift serial (SR SER, SL SER) inputs, operatingmode-control (S0, S1) inputs, and a direct overriding clear (CLR

) line. The registers have

four distinct modes of operation:

• Inhibit clock (temporary data latch/do nothing)

• Shift right (in the direction Q

toward QD)

• Shift left (in the direction Q

toward QA)

• Parallel (broadside) load

Parallel synchronous loading is accomplished by applying the four bits of data and taking both S0 and S1 high. The data is loaded into the associated flip-flops and appears at the outputs after the positive transition of the clock (CLK) input. During loading, serial data flow is inhibited.

Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low. Serial data for this mode is entered at the shift-right data input. When S0 is low and S1 is high, data shifts left synchronously and new data is entered at the shift-left serial inputs. Clocking of the flip-flop is inhibited when both mode-control inputs are low.

The SN54AS194 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74AS194 is characterized for operation from 0°C to 70°C.

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10

CLR

SR SER

A B C D

SL SER

GND

CLK S1 S0

SN54AS194 ...J PACKAGE

SN74AS194 ...D OR N PACKAGE

(TOP VIEW)

3212019

910111213

4 5 6 7 8

18 17 16 15 14

NC Q

CLK

A B

C D

SR SER

CLR

SL SER

GND

NC – No internal connection

SN54AS194 ...FK PACKAGE

(TOP VIEW)

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

SN54AS194, SN74AS194 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS

SDAS212A – DECEMBER 1983 – REVISED DECEMBER 1994

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FUNCTION TABLE

INPUTS

OUTPUTS

MODE

SERIAL PARALLEL

CLR

S1 S0

CLK

LEFT RIGHT A B C D

QAQBQCQ

L X X X X X X X X X L L L L H X XLXXXXXXQA0Q

B0QC0QD0

H H H ↑ X Xabcdabcd HLH↑XHXXXXHQAnQ

BnQCn

H L H ↑ X LXXXXLQAnQ

BnQCn

H H L ↑ H XXXXXQBnQ

CnQDn

H H L ↑ L XXXXXQBnQ

CnQDn

H L L X X X X X X X Q

A0QB0QC0QD0

H = high level (steady state); L = low level (steady state); X = irrelevant (any input, including transitions); ↑ = transition from low to high level; a, b, c, d = the level of steady-state input at inputs A, B, C, or D, respectively; QA0, QB0, QC0, Q

= the level of QA, QB, QC, or QD, respectively, before the indicated steady-state input conditions were established; QAn, QBn, QCn, QDn = the level of QA, QB, QC, respectively, before the most recent ↑ transition of the clock.

logic symbol

†

SRG4

3, 4D

2, 4D

SL SER

1, 4D

SR SER

3, 4D

CLK

0 3

14 13

1 /2

CLR

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

SN54AS194, SN74AS194

4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS

SDAS212A – DECEMBER 1983 – REVISED DECEMBER 1994

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

Two

Identical

Channels

Not

Shown

†

SR SER

SL SER

CLR

CLK

1R R

15 12

Parallel Inputs

Parallel Outputs

†

I/O ports not shown: QB (14) and QC (13)

Pin numbers shown are for the D, J, and N packages.

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