Datasheet SN54AS194J, SN74AS194D, SN74AS194DR, SN74AS194N, SNJ54AS194FK Datasheet (Texas Instruments)
...
SN54AS194, SN74AS194
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
SDAS212A – DECEMBER 1983 – REVISED DECEMBER 1994
Copyright 1994, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
• Parallel-to-Serial, Serial-to-Parallel
Conversions
• Left or Right Shifts
• Parallel Synchronous Loading
• Direct Overriding Clear
• Temporary Data-Latching Capability
• Package Options Include Plastic
Small-Outline Packages (D), Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
These 4-bit bidirectional universal shift registers
feature parallel outputs, right-shift and left-shift
serial (SR SER, SL SER) inputs, operatingmode-control (S0, S1) inputs, and a direct
overriding clear (CLR
) line. The registers have
four distinct modes of operation:
• Inhibit clock (temporary data latch/do nothing)
• Shift right (in the direction Q
A
toward QD)
• Shift left (in the direction Q
D
toward QA)
• Parallel (broadside) load
Parallel synchronous loading is accomplished by
applying the four bits of data and taking both S0
and S1 high. The data is loaded into the
associated flip-flops and appears at the outputs
after the positive transition of the clock (CLK)
input. During loading, serial data flow is inhibited.
Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low.
Serial data for this mode is entered at the shift-right data input. When S0 is low and S1 is high, data shifts left
synchronously and new data is entered at the shift-left serial inputs. Clocking of the flip-flop is inhibited when
both mode-control inputs are low.
The SN54AS194 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74AS194 is characterized for operation from 0°C to 70°C.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLR
SR SER
A
B
C
D
SL SER
GND
V
CC
Q
A
Q
B
Q
C
Q
D
CLK
S1
S0
SN54AS194 ...J PACKAGE
SN74AS194 ...D OR N PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
Q
B
Q
C
NC
Q
D
CLK
A
B
NC
C
D
SR SER
CLR
NC
S0
S1
SL SER
GND
NC
NC – No internal connection
V
CC
Q
A
SN54AS194 ...FK PACKAGE
(TOP VIEW)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN54AS194, SN74AS194
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
SDAS212A – DECEMBER 1983 – REVISED DECEMBER 1994
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
OUTPUTS
MODE
SERIAL PARALLEL
CLR
S1 S0
CLK
LEFT RIGHT A B C D
QAQBQCQ
D
L X X X X X X X X X L L L L
H X XLXXXXXXQA0Q
B0QC0QD0
H H H ↑ X Xabcdabcd
HLH↑XHXXXXHQAnQ
BnQCn
H L H ↑ X LXXXXLQAnQ
BnQCn
H H L ↑ H XXXXXQBnQ
CnQDn
H
H H L ↑ L XXXXXQBnQ
CnQDn
L
H L L X X X X X X X Q
A0QB0QC0QD0
H = high level (steady state); L = low level (steady state); X = irrelevant (any input, including transitions); ↑ = transition from
low to high level; a, b, c, d = the level of steady-state input at inputs A, B, C, or D, respectively; QA0, QB0, QC0, Q
D0
= the
level of QA, QB, QC, or QD, respectively, before the indicated steady-state input conditions were established; QAn, QBn, QCn,
QDn = the level of QA, QB, QC, respectively, before the most recent ↑ transition of the clock.
logic symbol
†
SRG4
3, 4D
4
B
3, 4D
5
C
3, 4D
6
D
2, 4D
7
SL SER
1, 4D
2
SR SER
3, 4D
3
A
R
1
11
CLK
C4
M
0
3
14
13
15
1
10
S1
0
9
S0
1 /2
12
CLR
Q
A
Q
B
Q
C
Q
D
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
SN54AS194, SN74AS194
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
SDAS212A – DECEMBER 1983 – REVISED DECEMBER 1994
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
C1
1S
Two
Identical
Channels
Not
Shown
†
9
2
11
7
S0
S1
SR SER
SL SER
Q
A
Q
D
1
CLR
10
1R
CLK
R
C1
1S
1R
R
AD
36
15 12
Parallel Inputs
Parallel Outputs
†
I/O ports not shown: QB (14) and QC (13)
Pin numbers shown are for the D, J, and N packages.
SN54AS194, SN74AS194
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
SDAS212A – DECEMBER 1983 – REVISED DECEMBER 1994
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Shift Left
Clear
InhibitShift Right
Clear Load
L
H
L
H
Mode-
Control
Inputs
Serial
Data
Inputs
Parallel
Data
Inputs
Outputs
CLK
S0
S1
CLR
R
L
A
B
C
D
Q
A
Q
B
Q
C
Q
D
Figure 1. Typical Clear, Load, Right-Shift, and Clear Sequences
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage, V
CC
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
I
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
: SN54AS194 –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74AS194 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
SN54AS194, SN74AS194
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
SDAS212A – DECEMBER 1983 – REVISED DECEMBER 1994
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
SN54AS194 SN74AS194
MIN NOM MAX MIN NOM MAX
UNIT
V
CC
Supply voltage 4.5 5 5.5 4.5 5 5.5 V
V
IH
High-level input voltage 2 2 V
V
IL
Low-level input voltage 0.8 0.8 V
I
OH
High-level output current –2 –2 mA
I
OL
Low-level output current 20 20 mA
f
clock
* Clock frequency 0 75 0 80 MHz
CLR 4 4.5
tw* Pulse duration
CLK high
4 4
ns
CLK low 6 7
Select 9 9.5
tsu*
Setup time before CLK↑
Data
3.5 4
ns
Clear inactive state 6 6
th* Hold time, data after CLK↑ 0.5 0.5 ns
T
A
Operating free-air temperature –55 125 0 70 °C
* On products compliant to MIL-STD-883, Class B, these parameters are based on characterization data, but are not production tested.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54AS194 SN74AS194
PARAMETER
TEST CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
V
IK
VCC = 4.5 V, II = –18 mA –1.2 –1.2 V
V
OH
VCC = 4.5 V to 5.5 V, IOH = –2 mA VCC–2 VCC–2 V
V
OL
VCC = 4.5 V, IOL = 20 mA 0.35 0.5 0.35 0.5 V
Data, CLK, CLR
0.1 0.1
I
I
Mode, SL, SR
V
CC
= 5.5 V,
V
I
= 7
V
0.2 0.2
mA
Data, CLK, CLR
20 20
I
IH
Mode, SL, SR
V
CC
= 5.5 V,
V
I
= 2.7
V
40 40
µ
A
Data, CLK, CLR
–0.5 –0.5
I
IL
Mode, SL, SR
V
CC
= 5.5 V,
V
I
= 0.4
V
–1 –1
mA
I
O
‡
VCC = 5.5 V, VO = 2.25 V –30 –112 –30 –112 mA
Outputs high 30 49 30 43
ICCV
CC
=
5.5 V
Outputs low 38 60 38 53
mA
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
SN54AS194, SN74AS194
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
SDAS212A – DECEMBER 1983 – REVISED DECEMBER 1994
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics (see Figure 2)
PARAMETER
FROM
(
INPUT
)
TO
(
OUTPUT
)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500 Ω
,
TA = MIN to MAX
†
UNIT
(INPUT)
(OUTPUT)
SN54AS194 SN74AS194
MIN MAX MIN MAX
f
max
* 75 80 MHz
t
PLH
2.5 8 3 7
t
PHL
CLK
Any Q
2.5 8 3 7
ns
t
PHL
CLR Any Q 3.5 13 4 12 ns
* On products compliant to MIL-STD-883, Class B, these parameters are based on characterization data, but are not production tested.
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
SN54AS194, SN74AS194
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
SDAS212A – DECEMBER 1983 – REVISED DECEMBER 1994
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
t
PHZ
t
PLZ
t
PHL
t
PLH
0.3 V
t
PZL
t
PZH
t
PLH
t
PHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
From Output
Under Test
Test
Point
R1
S1
C
L
(see Note A)
7 V
1.3 V
1.3 V1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
t
h
t
su
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
1.3 V 1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
High-Level
Pulse
Low-Level
Pulse
t
w
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note C)
1.3 V 1.3 V
1.3 V1.3 V
1.3 V 1.3 V
1.3 V1.3 V
1.3 V
1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
V
OL
V
OH
V
OH
V
OL
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
[
0 V
V
OH
V
OL
[
3.5 V
In-Phase
Output
0.3 V
1.3 V 1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
R2
V
CC
R
L
Test
Point
From Output
Under Test
C
L
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
From Output
Under Test
Test
Point
C
L
(see Note A)
R
L
RL = R1 = R2
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 2. Load Circuits and Voltage Waveforms
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