Texas Instruments SN54AS181BJT, SN74AS181ADW, SN74AS181ADWR, SN74AS181AN, SN74AS181ANT Datasheet

SN54AS181B . . . JT OR JW PACKAGE

SN74AS181A ...N OR NT PACKAGE

(TOP VIEW)

SN54AS181B . . . FK PACKAGE

(TOP VIEW)

1
2
3
4
5
6
7
8
9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

B0
A0
S3
S2
S1
S0
C

n

M

F

0
F1
F

2

GND

V

CC

A1
B

1

A

2
B2
A

3
B3
G
C

n + 4

P
A = B
F3

NC – No internal connection

3212827

12 13

5
6
7
8
9
10
11

25
24
23
22
21
20
19

A2
B

2

A

3
NC
B

3
G
C

n + 4

S2
S1
S0

NC

C

n

M

F

0

426

14 15 16 17 18

F1

F2

GND

NC

F3

A = B

P

S3A0B0

NC

A1

B1

V

CC

SN54AS181B, SN74AS181A

ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS

SDAS209B – DECEMBER 1982 – REVISED DECEMBER 1994

Copyright  1994, Texas Instruments Incorporated

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

• Full Look Ahead for High-Speed Operations

on Long Words

• Arithmetic Operating Modes:

– Addition
– Subtraction
– Shift Operand A One Position
– Magnitude Comparison
– Twelve Other Arithmetic Operations

• Logic Function Modes:

– Exclusive-OR
– Comparator
– AND, NAND, OR, NOR

• Package Options Include Plastic

Small-Outline (N) Packages, Ceramic (FK)
Chip Carriers, Standard Plastic (NT) and
Ceramic (JT) 300-mil DIPs, and Ceramic
(JW) 600-mil DIPs

description

The SN54AS181B and SN74AS181A arithmetic
logic units (ALUs)/function generators have a
complexity of 75 equivalent gates on a monolithic
chip. These circuits perform 16 binary arithmetic
operations on two 4-bit words as shown in
T ables1 and 2. These operations are selected by
the four function-select (S0, S1, S2, and S3) lines
and include addition, subtraction, decrement, and
straight transfer. When performing arithmetic
manipulations, the internal carries are enabled by
applying a low-level voltage to the mode-control
(M) input. A full carry look-ahead scheme is used
to generate fast, simultaneous carry by means of
two cascade (G

and P) outputs for the four bits in

the package.
If high speed is not important, a ripple-carry (C

n

) input and a ripple-carry (C

n + 4

) output are available. The
ripple-carry delay is minimized so that arithmetic manipulations for small word lengths can be performed without
external circuitry.

The SN54AS181B and SN74AS181A accommodate active-high or active-low data if the pin designations are
interpreted as follows:

PIN NUMBER 2 1 23 22 21 20 19 18 9 10 11 13 7 16 15 17

Active-low data (Table 1) A0 B0 A1 B1 A2 B2 A3 B3 F0 F1 F2 F3 CnCn + 4P G
Active-high data (Table 2) A0 B0 A1 B1 A2 B2 A3 B3 F0 F1 F2 F3 CnCn + 4X Y

Subtraction is accomplished by 1’s complement addition where the 1’s complement of the subtrahend is
generated internally . The resultant output is A-B-1, which requires an end-around or forced carry to provide A-B.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

SN54AS181B, SN74AS181A
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS

SDAS209B – DECEMBER 1982 – REVISED DECEMBER 1994

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

The SN54AS181B and SN74AS181A also can be used as comparators. The A = B output is internally decoded
from the function (F0, F1, F2, F3) outputs so that when two words of equal magnitude are applied at the A and
B inputs, the output assumes a high level to indicate equality (A = B). The ALU must be in the subtract mode
with C

n

= H when performing this comparison. The A = B output is open collector so that it can be wire-AND

connected to give a comparison for more than four bits. C

n + 4

also can be used to supply relative magnitude
information. The ALU must be placed in the subtract mode by placing the function-select inputs S3, S2, S1, and
S0 at L, H, H, and L, respectively.

INPUT

C

n

OUTPUT

Cn +

4

ACTIVE-LOW DATA

(Figure 1)

ACTIVE-HIGH DATA

(Figure 2)

H H A ≥ B A ≤ B
H L A < B A > B
L H A > B A < B
L L A ≤ B A ≥ B

These circuits not only incorporate all of the designer’s requirements for arithmetic operations, but also provide
16 possible functions of two Boolean variables without using external circuitry. These logic functions are
selected by the four function-select inputs with M at a high level to disable the internal carry. The 16 logic
functions are detailed in Tables 1 and 2 and include exclusive-OR, NAND, AND, NOR, and OR functions.

TYPICAL ADDITION TIME

(CL = 15 pF, RL = 280 Ω, TA = 25°C)

ADDITION

PACKAGE COUNT

NUMBER

OF BITS

TIME USING

′S181 AND

′S182

ALUs

LOOK-AHEAD

CARRY

GENERAT ORS

CARRY METHOD

BETWEEN ALUs

1 to 4 11 ns 1 None
5 to 8 18 ns 2 Ripple

9 to 16 19 ns 3 or 4 1 Full look ahead

17 to 64 28 ns 5 to 16 2 to 5 Full look ahead

The SN54AS181B is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74AS181A is characterized for operation from 0°C to 70°C.

application note

An application-specific problem has been identified in the SN54AS181B device. The F0 –F4 outputs exhibit
voltage transients when one or more B-data inputs transition from a high to a low state. The resultant voltage
transients can have an amplitude of 2 V relative to V

OL

with a width of 5 ns at an input threshold of 1.5 V. The
transient pulse occurs coincidentally with the high-to-low transition of the B-data input(s) and appears to be
caused by internal coupling.

In system operations in which this device is used, it is likely that transmission-line effects minimize this anomaly .
Narrow width of the voltage transient makes the pulse transparent to most circuitry; however, in certain
applications, the transients can cause system errors.

SN54AS181B, SN74AS181A

ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS

SDAS209B – DECEMBER 1982 – REVISED DECEMBER 1994

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic symbol

†

M

0

31

0

6

S0

5

S1

4

S2

3

S3

4

8

M

15

A = B

14

C1

7

17

16

9

10

11

13

P

2

Q

1

P

23

Q

22

P

21

Q

20

P

19

Q

18

ALU

[1]

[2]

[3]

[8]

C

n

A

0

A

1

A

2

A3

B

0

B

1

B

2

B3

(0 . . . 15) CP

(0 . . . 15) CG

6(P=Q)

(0 . . . 15) CO

P
G

Cn +

4

F

0

F1

F2

F

3

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the JT, JW, N, and NT packages.

SN54AS181B, SN74AS181A
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS

SDAS209B – DECEMBER 1982 – REVISED DECEMBER 1994

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram

C

n

A

0

A

1

A

2

A

3

B

0

B

1

B

2

B

3

P

G

Cn +

4

F

0

F

1

F

2

F

3

S3
S2

S1
S0

M

3
4

5
6

18

19

20

21

22

23

1

2
8
7

A = B

17

16

15

13

11

14

10

9

Pin numbers shown are for the JT, JW, N, and NT packages.