Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic (N)
and Ceramic (J) 300-mil DIPs
description
These identity comparators perform comparisons
on two 8-bit binary or BCD words and provide
P = Q
outputs. These devices have totem-pole
outputs.
The SN54ALS688 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74ALS688 is characterized for
operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
DATA
ENABLE
P, Q
P = QLL
P > QLH
P < QLH
XHH
G
P = Q
SN54ALS688 ...J PACKAGE
SN74ALS688 ...DW OR N PACKAGE
SN54ALS688 . . . FK PACKAGE
P1
Q1
P2
Q2
P3
(TOP VIEW)
G
1
P0
2
Q0
3
P1
4
Q1
5
P2
6
Q2
7
P3
8
9
Q3
GND
10
(TOP VIEW)
Q0P0G
3212019
4
5
6
7
8
910111213
Q3
P4
20
19
18
17
16
15
14
13
12
11
V
CC
Q4
V
CC
P = Q
Q7
P7
Q6
P6
Q5
P5
Q4
P4
18
17
16
15
14
P5P = Q
Q7
P7
Q6
P6
Q5
GND
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1995, Texas Instruments Incorporated
1
SN54ALS688, SN74ALS688
8-BIT IDENTITY COMPARATORS
SDAS228A – JUNE 1982 – REVISED JANUAR Y 1995
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
†
G1
0
7
0
7
COMP
P
1P=Q
Q
P0
P1
P2
P3
P4
P5
P6
P7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
1
G
2
4
6
8
11
13
15
17
3
5
7
9
12
14
16
18
19
P = Q
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
17
P7
18
Q7
15
P6
16
Q6
13
P5
14
Q5
11
P4
12
Q4
8
P3
SN54ALS688, SN74ALS688
8-BIT IDENTITY COMPARATORS
SDAS228A – JUNE 1982 – REVISED JANUARY 1995
19
P = Q
9
Q3
6
P2
7
Q2
4
P1
5
Q1
2
P0
3
Q0
1
G
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
Input voltage, V
Operating free-air temperature range, T
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
PHL
FROM
INPUT
TO
OUTPUT
=
=
=
RL = 500 Ω
TA = MIN to MAX
SN54ALS688 SN74ALS688
MINMAXMINMAX
316312
525520
316312
525520
315312
525522
,
§
UNIT
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
(see Note A)
SN54ALS688, SN74ALS688
8-BIT IDENTITY COMPARATORS
SDAS228A – JUNE 1982 – REVISED JANUARY 1995
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7 V
V
CC
S1
R
L
Test
Point
C
L
R
L
From Output
Under Test
C
(see Note A)
Test
Point
L
From Output
Under Test
(see Note A)
R1
C
L
RL = R1 = R2
Test
Point
R2
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
Timing
Input
t
su
Data
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
t
PZL
t
PZH
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
1.3 V
t
PHZ
1.3 V
1.3 V
t
1.3 V1.3 V
1.3 V1.3 V
FOR OPEN-COLLECTOR OUTPUTS
h
t
PLZ
LOAD CIRCUIT
3.5 V
0.3 V
3.5 V
0.3 V
3.5 V
0.3 V
[
3.5 V
V
OL
0.3 V
V
OH
0.3 V
[
0 V
High-Level
Low-Level
Out-of-Phase
(see Note C)
Pulse
Pulse
Input
In-Phase
Output
Output
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
1.3 V1.3 V
t
w
1.3 V1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.3 V1.3 V
t
PLH
t
PHL
1.3 V1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.3 V1.3 V
t
PHL
t
PLH
3.5 V
0.3 V
3.5 V
0.3 V
3.5 V
0.3 V
V
V
V
V
OH
OL
OH
OL
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
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