Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
These devices contain four independent 2-input
positive-NOR buffers with open-collector outputs.
Open-collector outputs require resistive pullup to
perform correctly. They can deliver higher V
levels and commonly are used in wired-AND
applications. These devices perform the Boolean
functions Y = A
The SN54ALS33A is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74ALS33A is characterized for
operation from 0°C to 70°C.
• B or Y = A + B in positive logic.
FUNCTION TABLE
(each gate)
INPUTS
AB
HXL
XHL
LLH
OUTPUT
Y
OH
SN54ALS33A ...J PACKAGE
SN74ALS33A ...D OR N PACKAGE
SN54ALS33A . . . FK PACKAGE
1B
NC
2Y
NC
2A
NC – No internal connection
(TOP VIEW)
1Y
1
1A
2
1B
3
2Y
4
2A
5
2B
6
GND
7
(TOP VIEW)
1A1YNC
3212019
4
5
6
7
8
910111213
2B
NC
GND
14
13
12
11
10
V
CC
4Y
4B
4A
3Y
3B
9
3A
8
CC
V
4Y
4B
18
NC
17
4A
16
NC
15
3Y
14
3A
3B
2
3
5
6
8
9
11
12
†
≥1
1
4
10
13
logic symbol
1A
1B
2A
2B
3A
3B
4A
4B
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
logic diagram (positive logic)
1
1A
1Y
2Y
3Y
4Y
1B
2A
2B
3A
3B
4A
4B
2
4
5
9
10
12
13
3
1Y
6
2Y
8
3Y
11
4Y
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1994, Texas Instruments Incorporated
1
SN54ALS33A, SN74ALS33A
UNIT
PARAMETER
TEST CONDITIONS
UNIT
V
V
V
V
(
)
(
)
(INPUT)
(OUTPUT)
A or B
Y
ns
QUADRUPLE 2-INPUT POSITIVE-NOR BUFFERS
WITH OPEN-COLLECTOR OUTPUTS
SDAS034B – APRIL 1982 – REVISED DECEMBER 1994
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
2
PHL
FROM
INPUT
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
OUTPUT
TO
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 680 Ω,
TA = MIN to MAX
SN54ALS33A SN74ALS33A
MINMAXMINMAX
10591033
218212
§
UNIT
From Output
Under Test
(see Note A)
SN54ALS33A, SN74ALS33A
QUADRUPLE 2-INPUT POSITIVE-NOR BUFFERS
WITH OPEN-COLLECTOR OUTPUTS
SDAS034B – APRIL 1982 – REVISED DECEMBER 1994
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7 V
V
CC
S1
R
L
Test
Point
C
L
R
L
From Output
Under Test
(see Note A)
Test
Point
C
L
From Output
Under Test
(see Note A)
R1
C
L
RL = R1 = R2
Test
Point
R2
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
Timing
Input
t
su
Data
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
t
PZL
t
PZH
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
1.3 V
t
PHZ
1.3 V
1.3 V
t
1.3 V1.3 V
1.3 V1.3 V
FOR OPEN-COLLECTOR OUTPUTS
h
t
PLZ
LOAD CIRCUIT
3.5 V
0.3 V
3.5 V
0.3 V
3.5 V
0.3 V
[
3.5 V
V
OL
0.3 V
V
OH
0.3 V
[
0 V
High-Level
Low-Level
Out-of-Phase
(see Note C)
Pulse
Pulse
Input
In-Phase
Output
Output
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
1.3 V1.3 V
t
w
1.3 V1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.3 V1.3 V
t
PLH
t
PHL
1.3 V1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.3 V1.3 V
t
PHL
t
PLH
3.5 V
0.3 V
3.5 V
0.3 V
3.5 V
0.3 V
V
V
V
V
OH
OL
OH
OL
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.