TEXAS INSTRUMENTS SN54ALS33A Technical data

SN54ALS33A, SN74ALS33A

QUADRUPLE 2-INPUT POSITIVE-NOR BUFFERS

WITH OPEN-COLLECTOR OUTPUTS

SDAS034B – APRIL 1982 – REVISED DECEMBER 1994

• Package Options Include Plastic

Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs

description

These devices contain four independent 2-input
positive-NOR buffers with open-collector outputs.
Open-collector outputs require resistive pullup to
perform correctly. They can deliver higher V
levels and commonly are used in wired-AND
applications. These devices perform the Boolean
functions Y = A

The SN54ALS33A is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74ALS33A is characterized for
operation from 0°C to 70°C.

• B or Y = A + B in positive logic.

FUNCTION TABLE
(each gate)

INPUTS

A B

H X L
X HL

LLH

OUTPUT

Y

OH

SN54ALS33A ...J PACKAGE

SN74ALS33A ...D OR N PACKAGE

SN54ALS33A . . . FK PACKAGE

1B

NC

2Y

NC

2A

NC – No internal connection

(TOP VIEW)

1Y

1

1A

2

1B

3

2Y

4

2A

5

2B

6

GND

7

(TOP VIEW)

1A1YNC

3212019

4
5
6
7
8

910111213

2B

NC

GND

14
13
12
11
10

V

CC

4Y
4B
4A
3Y
3B

9

3A

8

CC

V

4Y

4B

18

NC

17

4A

16

NC

15

3Y

14

3A

3B

2
3
5
6
8
9
11
12

†

≥1

1

4

10

13

logic symbol

1A
1B
2A
2B
3A
3B
4A
4B

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.

Pin numbers shown are for the D, J, and N packages.

logic diagram (positive logic)

1

1A

1Y

2Y

3Y

4Y

1B
2A

2B

3A
3B

4A
4B

2
4

5

9
10

12
13

3

1Y

6

2Y

8

3Y

11

4Y

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1994, Texas Instruments Incorporated

1

SN54ALS33A, SN74ALS33A

UNIT

PARAMETER

TEST CONDITIONS

UNIT

V

V

V

V

(

)

(

)

(INPUT)

(OUTPUT)

A or B

Y

ns

QUADRUPLE 2-INPUT POSITIVE-NOR BUFFERS
WITH OPEN-COLLECTOR OUTPUTS

SDAS034B – APRIL 1982 – REVISED DECEMBER 1994

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, V
Input voltage, V

7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

†

Off-state output voltage 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

: SN54ALS33A –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A

SN74ALS33A 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

SN54ALS33A SN74ALS33A

MIN NOM MAX MIN NOM MAX

V
V
V
V
I
T

CC
IH
IL
OH

OL

A

Supply voltage 4.5 5 5.5 4.5 5 5.5 V
High-level input voltage 2 2 V
Low-level input voltage 0.7 0.8 V
High-level output voltage 5.5 5.5 V
Low-level output current 12 24 mA
Operating free-air temperature –55 125 0 70 °C

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

SN54ALS33A SN74ALS33A

MIN TYP‡MAX MIN TYP‡MAX

V

IK

OL

I

I

I

IH

I

IL

I

OH

I

CCH

I

‡

All typical values are at VCC = 5 V, TA = 25°C.

CCL

VCC = 4.5 V, II = –18 mA –1.5 –1.5 V

= 4.5

CC

VCC = 5.5 V, VI = 7 V 0.1 0.1 mA
VCC = 5.5 V, VI = 2.7 V 20 20 µA
VCC = 5.5 V, VI = 0.4 V –0.1 –0.1 mA
VCC = 4.5 V, VOH = 5.5 V 0.1 0.1 mA
VCC = 5.5 V, VI = 0 1.7 2.8 1.7 2.8 mA
VCC = 5.5 V, VI = 4.5 V 5.6 9 5.6 9 mA

IOL = 12 mA 0.25 0.4 0.25 0.4
IOL = 24 mA 0.35 0.5

switching characteristics (see Figure 1)

PARAMETER

t

PLH

t

§

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

2

PHL

FROM
INPUT

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

OUTPUT

TO

VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 680 Ω,
TA = MIN to MAX

SN54ALS33A SN74ALS33A

MIN MAX MIN MAX

10 59 10 33

2 18 2 12

§

UNIT

From Output

Under Test

(see Note A)

SN54ALS33A, SN74ALS33A

QUADRUPLE 2-INPUT POSITIVE-NOR BUFFERS

WITH OPEN-COLLECTOR OUTPUTS

SDAS034B – APRIL 1982 – REVISED DECEMBER 1994

PARAMETER MEASUREMENT INFORMATION

SERIES 54ALS/74ALS AND 54AS/74AS DEVICES

7 V

V

CC

S1

R

L

Test
Point

C

L

R

L

From Output

Under Test

(see Note A)

Test
Point

C

L

From Output

Under Test

(see Note A)

R1

C

L

RL = R1 = R2

Test
Point

R2

LOAD CIRCUIT FOR

BI-STATE

TOTEM-POLE OUTPUTS

Timing

Input

t

su

Data

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Output

Control

(low-level

enabling)

Waveform 1

S1 Closed

(see Note B)

Waveform 2

S1 Open

(see Note B)

t

PZL

t

PZH

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

VOLTAGE WAVEFORMS

1.3 V

t

PHZ

1.3 V

1.3 V

t

1.3 V1.3 V

1.3 V1.3 V

FOR OPEN-COLLECTOR OUTPUTS

h

t

PLZ

LOAD CIRCUIT

3.5 V

0.3 V

3.5 V

0.3 V

3.5 V

0.3 V

[

3.5 V

V

OL

0.3 V

V

OH

0.3 V

[

0 V

High-Level

Low-Level

Out-of-Phase

(see Note C)

Pulse

Pulse

Input

In-Phase

Output

Output

LOAD CIRCUIT

FOR 3-STATE OUTPUTS

1.3 V 1.3 V

t

w

1.3 V 1.3 V

VOLTAGE WAVEFORMS

PULSE DURATIONS

1.3 V 1.3 V

t

PLH

t

PHL

1.3 V 1.3 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

1.3 V1.3 V

t

PHL

t

PLH

3.5 V

0.3 V

3.5 V

0.3 V

3.5 V

0.3 V

V

V

V

V

OH

OL

OH

OL

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuits and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

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Copyright © 2007, Texas Instruments Incorporated

PACKAGE OPTION ADDENDUM

www.ti.com

9-Oct-2007

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package
Drawing

Pins Package

Qty

Eco Plan

SN54ALS33AJ ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type

SN74ALS33AD ACTIVE SOIC D 14 50 Green (RoHS &

no Sb/Br)

SN74ALS33ADE4 ACTIVE SOIC D 14 50 Green (RoHS &

no Sb/Br)

SN74ALS33ADG4 ACTIVE SOIC D 14 50 Green (RoHS &

no Sb/Br)

SN74ALS33ADR ACTIVE SOIC D 14 2500 Green (RoHS &

no Sb/Br)

SN74ALS33ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS &

no Sb/Br)

SN74ALS33ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS &

no Sb/Br)

SN74ALS33AN ACTIVE PDIP N 14 25 Pb-Free

SN74ALS33AN3 OBSOLETE PDIP N 14 TBD Call TI Call TI

SN74ALS33ANE4 ACTIVE PDIP N 14 25 Pb-Free

SNJ54ALS33AFK NRND LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type

SNJ54ALS33AJ NRND CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(RoHS)

(RoHS)

(2)

Lead/Ball Finish MSLPeak Temp

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU N / A for Pkg Type

CU NIPDAU N / A for Pkg Type

(3)

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

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Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

TAPE AND REEL INFORMATION

11-Mar-2008

*All dimensions are nominal

Device Package

SN74ALS33ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

Type

Package

Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0 (mm) B0 (mm) K0 (mm) P1

(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Mar-2008

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

SN74ALS33ADR SOIC D 14 2500 346.0 346.0 33.0

Pack Materials-Page 2

MECHANICAL DATA

MLCC006B – OCTOBER 1996

FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

A SQ

B SQ

20

22

23

24

25

19

21

12826 27

12

1314151618 17

0.020 (0,51)

0.010 (0,25)

MIN

0.342
(8,69)

0.442

0.640

0.739

0.938

1.141

A

0.358
(9,09)

0.458

(11,63)

0.660

(16,76)

0.761

(19,32)(18,78)

0.962

(24,43)

1.165

(29,59)

NO. OF

TERMINALS

**

11

10

9

8

7

6

5

432

20

28

44

52

68

84

0.020 (0,51)

0.010 (0,25)

(11,23)

(16,26)

(23,83)

(28,99)

MINMAX

0.307
(7,80)

0.406

(10,31)

0.495

(12,58)

0.495

(12,58)

0.850
(21,6)

1.047
(26,6)

0.080 (2,03)

0.064 (1,63)

B

MAX

0.358
(9,09)

0.458

(11,63)

0.560

(14,22)

0.560

(14,22)

0.858
(21,8)

1.063
(27,0)

0.055 (1,40)

0.045 (1,14)

0.028 (0,71)

0.022 (0,54)

0.050 (1,27)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0.045 (1,14)

0.035 (0,89)

0.045 (1,14)

0.035 (0,89)

4040140/D 10/96