Texas Instruments SN54ALS323J, SN74ALS323DW, SN74ALS323DWR, SN74ALS323N, SNJ54ALS323FK Datasheet
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SN54ALS323, SN74ALS323
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH SYNCHRONOUS CLEAR AND 3-STATE OUTPUTS
SDAS267A – DECEMBER 1982 – REVISED DECEMBER 1994
Copyright 1994, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
• Multiplexed I/O Ports Provide Improved Bit
Density
• Four Modes of Operation:
– Hold (Store)
– Shift Right
– Shift Left
– Load Data
• Operate With Outputs Enabled or at High
Impedance
• 3-State Outputs Drive Bus Lines Directly
• Can Be Cascaded for n-Bit Word Lengths
• Synchronous Clear
• Applications:
– Stacked or Push-Down Registers
– Buffer Storage
– Accumulator Registers
• Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic (N)
and Ceramic (J) 300-mil DIPs
description
These 8-bit universal shift/storage registers
feature multiplexed input/output (I/O) ports to
achieve full 8-bit data handling in a 20-pin
package. Two function-select (S0, S1) inputs and
two output-enable (OE1
, OE2) inputs can be used
to choose the modes of operation listed in the
function table.
Synchronous parallel loading is accomplished by taking both S0 and S1 high. This places the 3-state outputs
in the high-impedance state and permits data applied on the I/O ports to be clocked into the register. Reading
out of the register can be accomplished while the outputs are enabled in any mode. Clearing occurs
synchronously when the clear (CLR
) input is low. Taking either OE1 or OE2 high disables the outputs but has
no effect on clearing, shifting, or storing data.
The SN54ALS323 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ALS323 is characterized for operation from 0°C to 70°C.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
S0
OE1
OE2
G/Q
G
E/Q
E
C/Q
C
A/Q
A
Q
A′
CLR
GND
V
CC
S1
SL
Q
H′
H/Q
H
F/Q
F
D/Q
D
B/Q
B
CLK
SR
SN54ALS323 ...J PACKAGE
SN74ALS323 . . . DW OR N PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
SL
Q
H′
H/Q
H
F/Q
F
D/Q
D
G/Q
G
E/Q
E
C/Q
C
A/Q
A
Q
A′
OE2
OE1
S0
CLK
B/Q
S1
CLR
GND
SR
V
CC
SN54ALS323 . . . FK PACKAGE
(TOP VIEW)
B
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN54ALS323, SN74ALS323
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH SYNCHRONOUS CLEAR AND 3-STATE OUTPUTS
SDAS267A – DECEMBER 1982 – REVISED DECEMBER 1994
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS I/O PORTS OUTPUTS
MODE
CLR S1 S0 OE1†OE2†CLK SL SR A/QAB/QBC/QCD/QDE/QEF/QFG/QGH/QHQA′Q
H′
Clear
L
L
L
X
L
H
L
X
H
L
L
X
L
L
X
↑
↑
↑
X
X
X
X
X
X
L
L
X
L
L
X
L
L
X
L
L
X
L
L
X
L
L
X
L
L
X
L
L
X
L
L
L
L
L
L
Hold
HHLXL
XLL
L
L
XLXXXXQ
A0
Q
A0
Q
B0
Q
B0
Q
C0
Q
C0
Q
D0
Q
D0
Q
E0
Q
E0
Q
F0
Q
F0
Q
G0
Q
G0
Q
H0
Q
H0
Q
A0
Q
A0
Q
H0
Q
H0
Shift
RightHHLLHHLL
L
L
↑↑XXHLHLQ
An
Q
An
Q
Bn
Q
Bn
Q
Cn
Q
Cn
Q
Dn
Q
Dn
Q
En
Q
En
Q
Fn
Q
Fn
Q
Gn
Q
Gn
HLQ
Gn
Q
Gn
Shift
LeftHHHHLL
L
L
L
L
↑↑HLXXQ
Bn
Q
Bn
Q
Cn
Q
Cn
Q
Dn
Q
Dn
Q
En
Q
En
Q
Fn
Q
Fn
Q
Gn
Q
Gn
Q
Hn
Q
Hn
HLQ
Bn
Q
Bn
H
L
Load H H H X X ↑ X X a b c d e f g h a h
NOTE: a ...h = the level of the steady-state input at inputs A through H, respectively. This data is loaded into the flip-flops while the flip-flop outputs
are isolated from the I/O terminals.
†
When one or both output-enable inputs are high, the eight I/O terminals are disabled to the high-impedance state; however, sequ ential operation
or clearing of the register is not affected.
logic symbol
‡
SRG8
M
0
3
4R
9
6
14
5
15
4
8
2
3
0
1
S0
1
19
S1
12
CLK
5, 13
1,4D
11
SR
3,4D
7
6, 13
3, 4D
13
17
12, 13
2, 4D
18
SL
3, 4D
16
&
3
EN13
C4/1→/2←
Q
A′
Q
H′
CLR
OE1
OE2
A/Q
A
H/Q
H
B/Q
B
C/Q
C
D/Q
D
E/Q
E
F/Q
F
G/Q
G
Z5
Z6
Z12
‡
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
SN54ALS323, SN74ALS323
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH SYNCHRONOUS CLEAR AND 3-STATE OUTPUTS
SDAS267A – DECEMBER 1982 – REVISED DECEMBER 1994
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
C1
1D
C1
1D
Six
Identical
Channels
Not
Shown
†
9
1
19
11
12
8
2
3
18
17
CLR
S0
S1
SR
(shift right
serial input)
CLK
Q
A′
OE1
OE2
SL
(shift left
serial input)
Q
H′
716
A/Q
A
H/Q
H
†
I/O ports not shown: B/QB (13), C/QC (6), D/QD (14), E/QE (5), F/QF (15), and G/QG (4).
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
‡
Supply voltage, V
CC
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
I
: All inputs 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O ports 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
: SN54ALS323 –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ALS323 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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