Texas Instruments SN54ALS259J, SN74ALS259D, SN74ALS259DR, SN74ALS259N Datasheet

SN54ALS259, SN74ALS259

8-BIT ADDRESSABLE LATCHES

SDAS217A – DECEMBER 1982 – REVISED DECEMBER 1994

Copyright  1994, Texas Instruments Incorporated

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

• 8-Bit Parallel-Out Storage Register

Performs Serial-to-Parallel Conversion With
Storage

• Asynchronous Parallel Clear

• Active-High Decoder

• Enable/Disable Input Simplifies Expansion

• Expandable for n-Bit Applications

• Four Distinct Functional Modes

• Package Options Include Plastic

Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs

description

These 8-bit addressable latches are designed for
general-purpose storage applications in digital
systems. Specific uses include working registers,
serial-holding registers, and active-high decoders
or demultiplexers. They are multifunctional
devices capable of storing single-line data in eight
addressable latches and being a 1-of-8 decoder or
demultiplexer with active-high outputs.

Four distinct modes of operation are selectable by
controlling the clear (CLR

) and enable (G) inputs
as shown in the function table. In the
addressable-latch mode, data at the data-in
terminal is written into the addressed latch. The
addressed latch follows the data input with all unaddressed latches remaining in their previous states. In the
memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. To
eliminate the possibility of entering erroneous data in the latches, G

should be held high (inactive) while the
address lines are changing. In the 1-of-8 decoding or demultiplexing mode, the addressed output follows the
level of the D input with all other outputs low. In the clear mode, all outputs are low and unaf fected by the address
and data inputs.

The SN54ALS259 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ALS259 is characterized for operation from 0°C to 70°C.

Function Tables

FUNCTION

INPUTS

OUTPUT OF

EACH

CLR G

ADDRESSED

LATCH

OTHER

OUTPUT

FUNCTION

H L D Q

iO

Addressable latch

H HQiOQ

iO

Memory
L LD L8-line demultiplexer
L H L L Clear

D = the level at the data input.
QiO = the level of Qi (i = Q, 1,...7 as appropriate) before the indicated
steady-state input conditions were established.

SN54ALS259 ...J PACKAGE

SN74ALS259 ...D OR N PACKAGE

(TOP VIEW)

3212019

910111213

4
5
6
7
8

18
17
16
15
14

G
D
NC
Q7
Q6

S2
Q0

NC

Q1
Q2

SN54ALS259 . . . FK PACKAGE

(TOP VIEW)

S1S0NC

Q4

Q5

CLR

Q3

GND

NC

NC – No internal connection

V

CC

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

9

S0
S1

S2
Q0
Q1
Q2
Q3

GND

V

CC

CLR
G
D
Q7
Q6
Q5
Q4

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

SN54ALS259, SN74ALS259
8-BIT ADDRESSABLE LATCHES

SDAS217A – DECEMBER 1982 – REVISED DECEMBER 1994

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Function Tables (Continued)

LATCH SELECTION

SELECT INPUTS

LATCH

S2 S1 S0

ADDRESSED

L L L 0
L LH 1
LHL 2
LHH 3
HLL 4
HLH 5
HHL 6
HHH 7

logic symbol

†

8M

0
7

0

1

S0

2

S1

2

3

S2

G8

14

Z10

15

Z9

13

D

9, 0D

Q0

4

G

CLR

10, 0R
9, 1D

Q1

5

10, 1R
9, 2D

Q2

6

10, 2R
9, 3D

Q3

7

10, 3R
9, 4D

Q4

9

10, 4R
9, 5D

Q5

10

10, 5R
9, 6D

Q6

11

10, 6R
9, 7D

Q7

12

10, 7R

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, J, and N packages.

SN54ALS259, SN74ALS259

8-BIT ADDRESSABLE LATCHES

SDAS217A – DECEMBER 1982 – REVISED DECEMBER 1994

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

14

13

1

2

3

15

12

11

10

9

7

6

5

4

G

D

S0

S1

S2

CLR

Q7

Q6

Q5

Q4

Q3

Q2

Q1

Q0

Pin numbers shown are for the D, J, and N packages.