Texas Instruments SN54ALS193AJ, SN74ALS193AD, SN74ALS193ADR, SN74ALS193AN, SNJ54ALS193AFK Datasheet
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SN54ALS193A, SN74ALS193A
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
WITH DUAL CLOCK AND CLEAR
SDAS211C – DECEMBER 1982 – REVISED JULY 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Look-Ahead Circuitry Enhances Cascaded
Counters
D
Fully Synchronous in Count Modes
D
Parallel Asynchronous Load for Modulo-N
Count Lengths
D
Asynchronous Clear
D
Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
The ’ALS193A are synchronous, reversible, 4-bit
up/down binary counters. Synchronous counting
operation is provided by having all flip-flops
clocked simultaneously so that the outputs
change coincident with each other when
instructed by the steering logic. This mode of
operation eliminates the output counting spikes
normally associated with asynchronous (rippleclock) counters.
The outputs of the four flip-flops are triggered on
a low-to-high-level transition of either count/clock
(UP or DOWN) input. The direction of the count is
determined by which count input is pulsed while
the other count input is high.
All four counters are fully programmable; that is, each output may be preset to either level by placing a low on
the load (LOAD
) input and entering the desired data at the data inputs. The output changes to agree with the
data inputs independently of the count pulses. This feature allows the counters to be used as modulo-N dividers
by simply modifying the count length with the preset inputs.
A high level applied to the clear (CLR) input forces all outputs to the low level. The clear function is independent
of the count and LOAD
inputs. The UP, DOWN, and LOAD inputs are buffered to lower the drive requirement,
which significantly reduces the loading on, or current required by, clock drivers, etc., for long parallel words.
These counters are designed to be cascaded without the need for external circuitry. The borrow (BO
) output
produces a low-level pulse while the count is zero (all Q outputs low) and the DOWN input is low. Similarily, the
carry (CO
) output produces a low-level pulse while the count is 9 or 15 (all Q outputs high) and the UP input
is low. The counters can then be easily cascaded by feeding BO
and CO to the count-down and count-up inputs,
respectively, of the succeeding counter.
The SN54ALS193A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ALS193A is characterized for operation from 0°C to 70°C.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
B
Q
B
Q
A
DOWN
UP
Q
C
Q
D
GND
V
CC
A
CLR
BO
CO
LOAD
C
D
SN54ALS193A ...J PACKAGE
SN74ALS193A ...D OR N PACKAGE
(TOP VIEW)
SN54ALS193A . . . FK PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
CLR
BO
NC
CO
LOAD
Q
A
DOWN
NC
UP
Q
C
B
NC
D
C
A
Q
GND
NC
D
Q
B
V
CC
NC – No internal connection
SN54ALS193A, SN74ALS193A
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
WITH DUAL CLOCK AND CLEAR
SDAS211C – DECEMBER 1982 – REVISED JULY 1996
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
CTRDIV16
LOAD
CO1CT = 15
2CT = 0
12
3D
15
A
1
B
10
C
9
D
CT = 0
14
CLR
2+
G1
C3
11
5
UP
1–
G2
4
DOWN
13
3
2
6
7
BO
Q
A
Q
B
Q
C
Q
D
[1]
[2]
[4]
[8]
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
SN54ALS193A, SN74ALS193A
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
WITH DUAL CLOCK AND CLEAR
SDAS211C – DECEMBER 1982 – REVISED JULY 1996
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
15
4
5
CO
A
1
10
9
B
C
D
UP
DOWN
Q
A
Q
B
Q
C
Q
D
12
13
3
2
6
7
1D
R
CLR
LOAD
S
R
S
R
R
R
1D
1D
1D
C1
C1
C1
C1
S
S
S
BO
14
11
Pin numbers shown are for the D, J, and N packages.
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