Texas Instruments SN54ALS191AJ, SN74ALS191AD, SN74ALS191ADR, SN74ALS191AN, SNJ54ALS191AFK Datasheet
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SN54ALS191A, SN74ALS191A
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
SDAS210C – DECEMBER 1982 – REVISED JUL Y 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Single Down/Up Count-Control Line
D
Look-Ahead Circuitry Enhances Speed of
Cascaded Counters
D
Fully Synchronous in Count Modes
D
Asynchronously Presettable With Load
Control
D
Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
The ’ALS191A are synchronous 4-bit reversible
up/down binary counters. Synchronous counting
operation is provided by having all flip-flops
clocked simultaneously so that the outputs
change coincidentally with each other when
instructed by the steering logic. This mode of
operation eliminates the output counting spikes
normally associated with asynchronous
(ripple-clock) counters.
The outputs of the four flip-flops are triggered on
a low-to-high-level transition of the clock (CLK)
input if the count enable (CTEN
) input is low. A
high at CTEN
inhibits counting. The direction of
the count is determined by the level of the
down/up (D/U
) input. When D/U is low, the counter
counts up, and when D/U
is high, the counter
counts down.
These counters feature a fully independent clock circuit. Changes at the control inputs (CTEN
and D/U) that
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter is dictated solely by the conditions meeting the stable setup and hold times.
These counters are fully programmable. Each output can be preset to either level by placing a low on the LOAD
input and entering the desired data at the data inputs. The output changes to agree with the data inputs
independently of the level of the clock input. This feature allows the counters to be used as modulo-N dividers
by simply modifying the count length with the preset inputs.
CLK, D/U
, and LOAD are buffered to lower the drive requirement, which significantly reduces the loading on
(current required by) clock drivers, for long parallel words.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
B
Q
B
Q
A
CTEN
D/U
Q
C
Q
D
GND
V
CC
A
CLK
RCO
MAX/MIN
LOAD
C
D
SN54ALS191A ...J PACKAGE
SN74ALS191A ...D OR N PACKAGE
(TOP VIEW)
SN54ALS191A . . . FK PACKAGE
(TOP VIEW)
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
CLK
RCO
NC
MAX/MIN
LOAD
Q
A
CTEN
NC
D/U
Q
C
B
NC
D
C
A
Q
GND
NC
D
Q
B
V
CC
NC – No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54ALS191A, SN74ALS191A
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
SDAS210C – DECEMBER 1982 – REVISED JUL Y 1996
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
Two outputs are available to perform the cascading function: ripple clock and maximum/minimum count. The
latter output produces a high-level output pulse with a duration approximately equal to one complete cycle of
the clock while the count is minimum (0) counting down or maximum (15) counting up. The ripple-clock output
(RCO
) produces a low-level output pulse under those same conditions, but only while the clock input is low. The
counter easily can be cascaded by feeding the ripple-clock output to the enable input of the succeeding counter
if parallel clocking is used, or to the clock input if parallel enabling is used. The maximum/minimum count
(MAX/MIN) output can be used to accomplish look ahead for high-speed operation.
The SN54ALS191A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ALS191A is characterized for operation from 0°C to 70°C.
logic symbol
†
1,2– / 1,3+
CTRDIV16
M2 [DOWN]
5
M3 [UP]
14
CLK
G4
C5
11
MAX/MIN
12
2(CT=0)Z6
3(CT=15)Z6
13
6,1,4
3
2
6
7
5D
15
A
1
B
10
C
9
D
G1
4
[1]
[2]
[4]
[8]
CTEN
D/U
Q
A
Q
B
Q
C
Q
D
LOAD
RCO
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
SN54ALS191A, SN74ALS191A
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
SDAS210C – DECEMBER 1982 – REVISED JUL Y 1996
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
15
4
11
14
5
CLK
A
1
10
9
B
C
D
CTEN
D/U
LOAD
Q
B
Q
C
Q
D
2
6
7
MAX/
MIN
Q
A
12
13
3
RCO
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
Pin numbers shown are for the D, J, and N packages.
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