Texas Instruments SN54ALS151J, SN74ALS151D, SN74ALS151DR, SN74ALS151N, SN74ALS151N3 Datasheet
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SN54ALS151, SN74ALS151, SN74AS151
OUTPUTS
1-OF-8 DATA SELECTORS/MULTIPLEXERS
SDAS205A – APRIL 1982 – REVISED DECEMBER 1994
• 8-Line to 1-Line Multiplexers Can Perform
as:
Boolean Function Generators
Parallel-to-Serial Converters
Data Source Selectors
• Input Clamping Diodes Simplify System
Design
• Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
These data selectors/multiplexers provide full
binary decoding to select one-of-eight data
sources. The strobe (G
logic level to enable the inputs. A high level at the
strobe terminal forces the W output high and the
Y output low.
The SN54ALS151 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74ALS151 and SN74AS151 are
characterized for operation from 0°C to 70°C.
) input must be at a low
SN74ALS151, SN74AS151 ...D OR N PACKAGE
SN54ALS151 ...J PACKAGE
(TOP VIEW)
D3
1
D2
2
D1
3
D0
4
Y
5
W
6
G
7
GND
SN54ALS151 . . . FK PACKAGE
8
(TOP VIEW)
D2D3NC
D1
D0
NC
3212019
4
5
6
7
Y
8
W
910111213
16
15
14
13
12
11
10
9
V
CC
V
D4
D5
D6
D7
A
B
C
D4
18
17
16
15
14
CC
D5
D6
NC
D7
A
NC – No internal connection
FUNCTION TABLE
INPUTS
SELECT
C B A
X X X H L H
L LL L D0 D0
L LH L D1 D1
L HL L D2 D2
L HH L D3 D3
H LL L D4 D4
H LH L D5 D5
H HL L D6 D6
H H H L D7 D7
H = high level, L = low level, X = irrelevant
D0, D1, . . . D7 = the level of the respective D input
STROBE
G
Y W
B
GND
NC
C
G
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1994, Texas Instruments Incorporated
1
SN54ALS151, SN74ALS151, SN74AS151
1-OF-8 DATA SELECTORS/MULTIPLEXERS
SDAS205A – APRIL 1982 – REVISED DECEMBER 1994
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
†
EN
0
2
0
1
2
3
4
5
6
7
MUX
G
0
7
D0
D1
D2
D3
D4
D5
D6
D7
7
G
11
A
10
B
9
C
4
3
2
1
15
14
13
12
logic diagram (positive logic)
7
G
4
D0
5
Y
6
W
3
D1
2
D2
1
Data
Inputs
Data
Select
(binary)
Pin numbers shown are for the D, J, and N packages.
D3
D4
D5
D6
D7
15
14
13
12
11
A
10
B
9
C
5
Y
6
W
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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