TEXAS INSTRUMENTS SN54AHCT86 Technical data

SOIC

D

AHCT86

TSSOP

PW

HB86

D

Inputs Are TTL-Voltage Compatible

D

Latch-Up Performance Exceeds 250 mA Per JESD 17

SN54AHCT86, SN74AHCT86

QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES

SCLS250M – OCTOBER 1995 – REVISED JUL Y 2003

D

ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A)

SN54AHCT86 ...J OR W PACKAGE SN74AHCT86 . . . D, DB, DGV, N, NS,

OR PW PACKAGE

(TOP VIEW)

1A

1

1B

2

1Y

3

2A

4

2B

5

2Y

6

GND

7

14 13 12 11 10

V

CC

4B 4A 4Y 3B 3A

9

3Y

8

SN74AHCT86 . . . RGY PACKAGE

1B 1Y 2A 2B 2Y

(TOP VIEW)

1A

114 2 3 4 5 6

78

CC

V

13 12 11 10

4B 4A 4Y 3B

9

3A

3Y

GND

SN54AHCT86 . . . FK PACKAGE

(TOP VIEW)

1B1ANC

1Y

NC

2A

NC

2B

NC – No internal connection

3212019

4 5 6 7 8

910111213

2Y

NC

GND

description/ordering information

The ’AHCT86 devices are quadruple 2-input exclusive-OR gates. These devices perform the Boolean function Y = A ⊕ B or Y = A

–40°C to 85°C

–55°C to 125°C

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.

B + AB in positive logic.

T

A

QFN – RGY Tape and reel SN74AHCT86RGYR HB86 PDIP – N Tube SN74AHCT86N SN74AHCT86N

–

SOP – NS Tape and reel SN74AHCT86NSR AHCT86 SSOP – DB Tape and reel SN74AHCT86DBR HB86

TVSOP – DGV Tape and reel SN74AHCT86DGVR HB86 CDIP – J Tube SNJ54AHCT86J SNJ54AHCT86J CFP – W Tube SNJ54AHCT86W SNJ54AHCT86W LCCC – FK Tube SNJ54AHCT86FK SNJ54AHCT86FK

ORDERING INFORMA TION

PACKAGE

–

†

Tube SN74AHCT86D Tape and reel SN74AHCT86DR

Tube SN74AHCT86PW Tape and reel SN74AHCT86PWR

ORDERABLE

PART NUMBER

TOP-SIDE MARKING

CC

V

3Y

4B

18 17 16 15 14

3A

4A NC 4Y NC 3B

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  2003, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

1

SN54AHCT86, SN74AHCT86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES

SCLS250M – OCTOBER 1995 – REVISED JULY 2003

FUNCTION TABLE

(each gate)

INPUTS

A B

L L L

L HH H LH H H L

exclusive-OR logic

An exclusive-OR gate has many applications, some of which can be represented better by alternative logic symbols.

EXCLUSIVE OR

= 1

These are five equivalent exclusive-OR symbols valid for an SN74AHCT86 gate in positive logic; negation may be shown at any two ports.

OUTPUT

Y

LOGIC-IDENTITY ELEMENT EVEN-PARITY ELEMENT ODD-PARITY ELEMENT

= 2k 2k + 1

The output is active (low) if all inputs stand at the same logic level (i.e., A = B).

The output is active (low) if an even number of inputs (i.e., 0 or 2) are active.

The output is active (high) if an odd number of inputs (i.e., only 1 of the 2) are active.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V Input voltage range, V Output voltage range, V Input clamp current, I Output clamp current, I Continuous output current, I Continuous current through V Package thermal impedance, θ

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

3. The package thermal impedance is calculated in accordance with JESD 51-5.

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

(V

< 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

I

(V

OK

< 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

(V

= 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 2): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

(see Note 2): DB package 96°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 2): DGV package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 2): N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 2): NS package 76°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 2): PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 3): RGY package 47°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

†

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UNIT

PARAMETER

TEST CONDITIONS

V

UNIT

V

4.5 V

V

4.5 V

V

PARAMETER

UNIT

A or B

Y

C

15 pF

ns

A or B

Y

C

50 pF

ns

SN54AHCT86, SN74AHCT86

QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES

SCLS250M – OCTOBER 1995 – REVISED JULY 2003

recommended operating conditions (see Note 4)

SN54AHCT86 SN74AHCT86

MIN MAX MIN MAX

V V V V V I

OH

I

OL

∆t/∆v Input transition rise or fall rate 20 20 ns/V T

NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.

†

This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC.

Supply voltage 4.5 5.5 4.5 5.5 V

CC

High-level input voltage 2 2 V

IH

Low-level input voltage 0.8 0.8 V

IL

Input voltage 0 5.5 0 5.5 V

I

Output voltage 0 V

O

High-level output current –8 –8 mA Low-level output current 8 8 mA

Operating free-air temperature –55 125 –40 85 °C

A

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

TA = 25°C SN54AHCT86 SN74AHCT86

MIN TYP MAX MIN MAX MIN MAX

4.4 4.5 4.4 4.4

3.94 3.8 3.8

0.1 0.1 0.1

0.36 0.44 0.44 I I

∆I C

OH

OL

I CC

i

CC

IOH = –50 mA IOH = –8 mA IOL = 50 mA IOL = 8 mA VI = 5.5 V or GND 0 V to 5.5 V ±0.1 ±1* ±1 VI = VCC or GND, IO = 0 5.5 V 2 20 20 One input at 3.4 V ,

†

Other inputs at VCC or GND VI = VCC or GND 5 V 4 10 10 pF

5.5 V 1.35 1.5 1.5 mA

CC

0 V

CC

V

m

A

m

A

switching characteristics over recommended operating free-air temperature range, V

= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)

CC

FROM TO LOAD

(INPUT) (OUTPUT) CAPACITANCE

t

PLH

t

PHL

t

PLH

t

PHL

** On products compliant to MIL-PRF-38535, this parameter is not production tested.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

p

=

L

p

=

L

TA = 25°C SN54AHCT86 SN74AHCT86

MIN TYP MAX MIN MAX MIN MAX

5** 6.9** 1** 8** 1 8 5** 6.9** 1** 8** 1 8

5.5 8.8 1 10 1 10

3

SN54AHCT86, SN74AHCT86

PARAMETER

UNIT

QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES

SCLS250M – OCTOBER 1995 – REVISED JULY 2003

noise characteristics, V

V

OL(P)

V

OL(V)

V

OH(V)

V

IH(D)

V

IL(D)

NOTE 5: Characteristics are for surface-mount packages only.

Quiet output, maximum dynamic V Quiet output, minimum dynamic V Quiet output, minimum dynamic V High-level dynamic input voltage 2 V Low-level dynamic input voltage 0.8 V

operating characteristics, V

C

Power dissipation capacitance No load, f = 1 MHz 18 pF

pd

= 5 V, CL = 50 pF, TA = 25°C (see Note 5)

CC

OL OL OH

= 5 V, TA = 25°C

CC

PARAMETER TEST CONDITIONS TYP UNIT

SN74AHCT86

MIN TYP MAX

0.4 0.8 V

–0.4 –0.8 V

4.4 V

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

From Output

Under Test

(see Note A)

SN54AHCT86, SN74AHCT86

QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES

SCLS250M – OCTOBER 1995 – REVISED JULY 2003

PARAMETER MEASUREMENT INFORMATION

V

Test Point

C

L

From Output

Under Test

(see Note A)

C

L

RL = 1 kΩ

S1

CC

Open

GND

TEST S1

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

Open Drain

Open

V

CC

GND V

CC

LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS

t

w

Input

In-Phase

Output

Out-of-Phase

Output

INVERTING AND NONINVERTING OUTPUTS

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. All parameters and waveforms are not applicable to all devices.

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

t

PLH

50% V

CC

t

PHL

50% V

CC

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

3-STATE AND OPEN-DRAIN OUTPUTS

LOAD CIRCUIT FOR

3 V

0 V

3 V

0 V

t

PHL

V

t

PLH

CC

V

CC

V

OH

OL

OH

OL

50% V

Timing Input

Data Input

Output

Control

Output

Waveform 1

S1 at V

(see Note B)

Waveform 2

(see Note B)

CC

Output

S1 at GND

1.5 V

t

CC

h

t

PLZ

VOL + 0.3 V

t

PHZ

VOH – 0.3 V

t

su

1.5 V 1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

1.5 V 1.5 V1.5 V 1.5 V

t

PZL

50% V

t

PZH

50% V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

3 V

0 V

3 V

0 V

3 V

0 V

≈V

V

OL

V

OH

≈0 V

CC

Figure 1. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

PACKAGE OPTION ADDENDUM

www.ti.com

PACKAGING INFORMATION

Orderable Device Status

5962-9681701Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type 5962-9681701QCA ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type 5962-9681701QDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type

SN74AHCT86D ACTIVE SOIC D 14 50 Green (RoHS &

SN74AHCT86DBLE OBSOLETE SSOP DB 14 TBD Call TI Call TI

SN74AHCT86DBR ACTIVE SSOP DB 14 2000 Green (RoHS &

SN74AHCT86DBRE4 ACTIVE SSOP DB 14 2000 Green (RoHS &

SN74AHCT86DE4 ACTIVE SOIC D 14 50 Green (RoHS &

SN74AHCT86DG4 ACTIVE SOIC D 14 50 Green (RoHS &

SN74AHCT86DGVR ACTIVE TVSOP DGV 14 2000 Green (RoHS &

SN74AHCT86DGVRE4 ACTIVE TVSOP DGV 14 2000 Green (RoHS &

SN74AHCT86DR ACTIVE SOIC D 14 2500 Green (RoHS &

SN74AHCT86DRE4 ACTIVE SOIC D 14 2500 Green (RoHS &

SN74AHCT86DRG4 ACTIVE SOIC D 14 2500 Green (RoHS &

SN74AHCT86N ACTIVE PDIP N 14 25 Pb-Free

SN74AHCT86NE4 ACTIVE PDIP N 14 25 Pb-Free

SN74AHCT86NSR ACTIVE SO NS 14 2000 Green (RoHS &

SN74AHCT86NSRE4 ACTIVE SO NS 14 2000 Green (RoHS &

SN74AHCT86PW ACTIVE TSSOP PW 14 90 Green (RoHS &

SN74AHCT86PWE4 ACTIVE TSSOP PW 14 90 Green (RoHS &

SN74AHCT86PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS &

SN74AHCT86PWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI

SN74AHCT86PWR ACTIVE TSSOP PW 14 2000 Green (RoHS &

SN74AHCT86PWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS &

SN74AHCT86PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS &

SN74AHCT86RGYR ACTIVE QFN RGY 14 1000 Green (RoHS &

SN74AHCT86RGYRG4 ACTIVE QFN RGY 14 1000 Green (RoHS &

(1)

Package

Type

Package Drawing

Pins Package

Qty

Eco Plan

no Sb/Br)

(RoHS)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU N/A for Pkg Type

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-2-260C-1YEAR

6-Dec-2006

(3)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device Status

(1)

Package

Type

Package Drawing

Pins Package

Qty

Eco Plan

(2)

Lead/Ball Finish MSL Peak Temp

6-Dec-2006

(3)

SNJ54AHCT86FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type

SNJ54AHCT86J ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type

SNJ54AHCT86W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

MECHANICAL DATA

MLCC006B – OCTOBER 1996

FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

A SQ

B SQ

19

20

21

22

23

24

25

12826 27

12

1314151618 17

0.020 (0,51)

0.010 (0,25)

MIN

0.342 (8,69)

0.442

0.640

0.739

0.938

1.141

A

0.358

(9,09)

0.458

(11,63)

0.660

(16,76)

0.761

(19,32)(18,78)

0.962

(24,43)

1.165

(29,59)

NO. OF

TERMINALS

**

11

10

9

8

7

6

5

432

20

28

44

52

68

84

0.020 (0,51)

0.010 (0,25)

(11,23)

(16,26)

(23,83)

(28,99)

MINMAX

0.307 (7,80)

0.406

(10,31)

0.495

(12,58)

0.495

(12,58)

0.850 (21,6)

1.047 (26,6)

0.080 (2,03)

0.064 (1,63)

B

MAX

0.358 (9,09)

0.458

(11,63)

0.560

(14,22)

0.560

(14,22)

0.858 (21,8)

1.063 (27,0)

0.055 (1,40)

0.045 (1,14)

0.028 (0,71)

0.022 (0,54)

0.050 (1,27)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated.

E. Falls within JEDEC MS-004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0.045 (1,14)

0.035 (0,89)

0.045 (1,14)

0.035 (0,89)

4040140/D 10/96