TEXAS INSTRUMENTS SN54AHCT125 Technical data

SOIC

D

AHCT125

TSSOP

PW

HB125

查询5962-9686901QDA供应商

D

Inputs Are TTL-Voltage Compatible

D

Latch-Up Performance Exceeds 250 mA Per JESD 17

SN54AHCT125, SN74AHCT125

QUADRUPLE BUS BUFFER GATES

WITH 3-STATE OUTPUTS

SCLS264O – DECEMBER 1995 – REVISED JUL Y 2003

D

ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101)

SN54AHCT125 ...J OR W PACKAGE SN74AHCT125 . . . D, DB, DGV, N, NS,

OR PW PACKAGE

(TOP VIEW)

1OE

1 2

1A

3

1Y

4

2OE

5

2A

6

2Y

GND

7

14 13 12 11 10

V

CC

4OE 4A 4Y 3OE

9

3A

8

3Y

SN74AHCT125 . . . RGY PACKAGE

1A 1Y

2OE

2A 2Y

(TOP VIEW)

1OE3YV

114 2 3 4 5 6

78

CC

13 12

10

4OE 4A

11

4Y 3OE

9

3A

GND

SN54AHCT125 . . . FK PACKAGE

1Y

NC

2OE

NC

2A

NC – No internal connection

(TOP VIEW)

1A

1OE

NC

3212019

4 5 6 7 8

910111213

2Y

NC

GND

description/ordering information

The ’AHCT125 devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE gate passes the data from the A input to its Y output.

T o ensure the high-impedance state during power up or power down, OE resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

ORDERING INFORMA TION

T

A

QFN – RGY Tape and reel SN74AHCT125RGYR HB125 PDIP – N Tube SN74AHCT125N SN74AHCT125N

–40°C to 85°C

–55°C to 125°C

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.

SOP – NS Tape and reel SN74AHCT125NSR AHCT125 SSOP – DB Tape and reel SN74AHCT125DBR HB125

TVSOP – DGV Tape and reel SN74AHCT125DGVR HB125 CDIP – J Tube SNJ54AHCT125J SNJ54AHCT125J CFP – W Tube SNJ54AHCT125W SNJ54AHCT125W LCCC – FK Tube SNJ54AHCT125FK SNJ54AHCT125FK

PACKAGE

–

†

Tube SN74AHCT125D Tape and reel SN74AHCT125DR

Tube SN74AHCT125PW Tape and reel SN74AHCT125PWR

) input is high. When OE is low, the respective

should be tied to VCC through a pullup

ORDERABLE

PART NUMBER

TOP-SIDE MARKING

CC

V

3Y

4OE

18 17 16 15 14

3A

4A NC 4Y NC 3OE

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  2003, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

1

SN54AHCT125, SN74AHCT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

SCLS264O – DECEMBER 1995 – REVISED JULY 2003

logic diagram (positive logic)

1

1OE

FUNCTION TABLE

(each buffer)

INPUTS

OE A

L H H L LL

H X Z

OUTPUT

Y

2

1A 1Y

4

2OE

5

2A 2Y

10

3OE

9

3A 3Y

13

4OE

12

4A 4Y

Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, RGY, and W packages.

3

6

8

11

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UNIT

SN54AHCT125, SN74AHCT125

QUADRUPLE BUS BUFFER GATES

WITH 3-STATE OUTPUTS

SCLS264O – DECEMBER 1995 – REVISED JULY 2003

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V Input voltage range, V Output voltage range, V Input clamp current, I Output clamp current, I Continuous output current, I Continuous current through V Package thermal impedance, θ

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

(V

< 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

I

(V

OK

< 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

(V

= 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 2): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

†

(see Note 2): DB package 96°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 2): DGV package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 2): N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 2): NS package 76°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 2): PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 3): RGY package 47°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

3. The package thermal impedance is calculated in accordance with JESD 51-5.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions (see Note 4)

SN54AHCT125 SN74AHCT125

MIN MAX MIN MAX

V V V V V I

OH

I

OL

∆t/∆v Input transition rise or fall rate 20 20 ns/V T

NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Supply voltage 4.5 5.5 4.5 5.5 V

CC

High-level input voltage 2 2 V

IH

Low-level input voltage 0.8 0.8 V

IL

Input voltage 0 5.5 0 5.5 V

I

Output voltage 0 V

O

High-level output current –8 –8 mA Low-level output current 8 8 mA

Operating free-air temperature –55 125 –40 85 °C

A

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

CC

0 V

CC

V

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

SN54AHCT125, SN74AHCT125

PARAMETER

TEST CONDITIONS

V

UNIT

V

4.5 V

V

4.5 V

V

PARAMETER

UNIT

AYC

15 pF

ns

OE

Y

C

15 pF

ns

OE

Y

C

15 pF

ns

AYC

50 pF

ns

OE

Y

C

50 pF

ns

OE

Y

C

50 pF

ns

PARAMETER

UNIT

QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

SCLS264O – DECEMBER 1995 – REVISED JULY 2003

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

CC

OH

OL

I

OZ

I

CC

∆I

CC

C

i

C

o

* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.

†

This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC.

IOH = –50 mA IOH = –8 mA IOL = 50 mA IOL = 8 mA VI = 5.5 V or GND 0 V to 5.5 V ±0.1 ±1* ±1 VO = VCC or GND 5.5 V ±0.25 ±2.5 ±2.5 VI = VCC or GND, IO = 0 5.5 V 2 20 20 One input at 3.4 V ,

†

Other inputs at VCC or GND VI = VCC or GND 5 V 4 10 10 pF VO = VCC or GND 5 V 15 pF

5.5 V 1.35 1.5 1.5 mA

TA = 25°C SN54AHCT125 SN74AHCT125

MIN TYP MAX MIN MAX MIN MAX

4.4 4.5 4.4 4.4

3.94 3.8 3.8

0.1 0.1 0.1

0.36 0.44 0.44

m

A

m

A

m

A

switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)

FROM TO LOAD

(INPUT) (OUTPUT) CAPACITANCE

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

t

sk(o)

** On products compliant to MIL-PRF-38535, this parameter is not production tested. *** On products compliant to MIL-PRF-38535, this parameter does not apply.

noise characteristics, V

V

OL(P)

V

OL(V)

V

OH(V)

V

IH(D)

V

IL(D)

NOTE 5: Characteristics are for surface-mount packages only.

Quiet output, maximum dynamic V Quiet output, minimum dynamic V Quiet output, minimum dynamic V High-level dynamic input voltage 2 V Low-level dynamic input voltage 0.8 V

= 5 V, CL = 50 pF, TA = 25°C (see Note 5)

CC

CL = 50 pF 1*** 1 ns

OL OL OH

p

=

L

p

=

L

p

=

L

p

=

L

p

=

L

p

=

L

TA = 25°C SN54AHCT125 SN74AHCT125

MIN TYP MAX MIN MAX MIN MAX

3.8** 5.5** 1** 6.5** 1 6.5

3.6** 5.1** 1** 6** 1 6

4.6** 6.8** 1** 8** 1 8

5.3 7.5 1 8.5 1 8.5

5.1 7.1 1 8 1 8

6.1 8.8 1 10 1 10

SN74AHCT125

MIN MAX

4.4 V

0.8 V

–0.8 V

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54AHCT125, SN74AHCT125

QUADRUPLE BUS BUFFER GATES

WITH 3-STATE OUTPUTS

SCLS264O – DECEMBER 1995 – REVISED JULY 2003

operating characteristics, V

C

Power dissipation capacitance No load, f = 1 MHz 14 pF

pd

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

(see Note A)

LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS

Input

Test Point

C

L

t

w

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

= 5 V, TA = 25°C

CC

PARAMETER TEST CONDITIONS TYP UNIT

V

CC

Open

GND

Open Drain

t

su

1.5 V 1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

TEST S1

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

1.5 V

t

h

Open

V

CC

GND V

CC

From Output

Under Test

C

(see Note A)

L

LOAD CIRCUIT FOR

3-STATE AND OPEN-DRAIN OUTPUTS

RL = 1 kΩ

3 V

0 V

S1

Timing Input

Data Input

3 V

0 V

3 V

0 V

Input

t

PLH

In-Phase

Output

t

PHL

Out-of-Phase

Output

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. All parameters and waveforms are not applicable to all devices.

50% V

CC

Figure 1. Load Circuit and Voltage Waveforms

t

PHL

50% V

t

PLH

50% V

CC

3 V

0 V

V

OH

OL

OH

OL

Output

Control

Output

Waveform 1

S1 at V

(see Note B)

Waveform 2

(see Note B)

CC

Output

S1 at GND

1.5 V 1.5 V1.5 V 1.5 V

t

PZL

50% V

CC

t

PZH

50% V

CC

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

t

PLZ

VOL + 0.3 V

t

PHZ

VOH – 0.3 V

3 V

0 V

≈V

V

OL

V

OH

≈0 V

CC

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

PACKAGE OPTION ADDENDUM

www.ti.com

PACKAGING INFORMATION

Orderable Device Status

5962-9686901Q2A ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NC 5962-9686901QCA ACTIVE CDIP J 14 1 TBD Call TI Level-NC-NC-NC 5962-9686901QDA ACTIVE CFP W 14 1 TBD Call TI Level-NC-NC-NC

SN74AHCT125D ACTIVE SOIC D 14 50 Green(RoHS &

SN74AHCT125DBLE OBSOLETE SSOP DB 14 TBD Call TI Call TI

SN74AHCT125DBR ACTIVE SSOP DB 14 2000 Green (RoHS &

SN74AHCT125DBRE4 ACTIVE SSOP DB 14 2000 Green (RoHS &

SN74AHCT125DE4 ACTIVE SOIC D 14 50 Green (RoHS &

SN74AHCT125DGVR ACTIVE TVSOP DGV 14 2000 Green (RoHS &

SN74AHCT125DGVRE4 ACTIVE TVSOP DGV 14 2000 Green (RoHS &

SN74AHCT125DR ACTIVE SOIC D 14 2500 Green (RoHS &

SN74AHCT125DRE4 ACTIVE SOIC D 14 2500 Green (RoHS &

SN74AHCT125N ACTIVE PDIP N 14 25 Pb-Free

SN74AHCT125NE4 ACTIVE PDIP N 14 25 Pb-Free

SN74AHCT125NSR ACTIVE SO NS 14 2000 Green (RoHS &

SN74AHCT125NSRE4 ACTIVE SO NS 14 2000 Green (RoHS &

SN74AHCT125PW ACTIVE TSSOP PW 14 90 Green (RoHS &

SN74AHCT125PWE4 ACTIVE TSSOP PW 14 90 Green (RoHS &

SN74AHCT125PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS &

SN74AHCT125PWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI

SN74AHCT125PWR ACTIVE TSSOP PW 14 2000 Green (RoHS &

SN74AHCT125PWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS &

SN74AHCT125PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS &

SN74AHCT125RGYR ACTIVE QFN RGY 14 1000 Green (RoHS &

SN74AHCT125RGYRG4 ACTIVE QFN RGY 14 1000 Green (RoHS &

SNJ54AHCT125FK ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NC

SNJ54AHCT125J ACTIVE CDIP J 14 1 TBD Call TI Level-NC-NC-NC

SNJ54AHCT125W ACTIVE CFP W 14 1 TBD Call TI Level-NC-NC-NC

(1)

Package

Type

Package

Drawing

Pins Package

Qty

Eco Plan

no Sb/Br)

(RoHS)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-NC-NC-NC

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-2-260C-1YEAR

24-Oct-2005

(3)

Addendum-Page 1