TEXAS INSTRUMENTS SN54AHC86 Technical data

SOIC
D
AHC86
TSSOP
PW
HA86
D
Operating Range 2-V to 5.5-V V
D
Latch-Up Performance Exceeds 250 mA Per JESD 17
SN54AHC86, SN74AHC86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCLS249I – OCTOBER 1995 – REVISED JUL Y 2003
D
ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101)
SN54AHC86 ...J OR W PACKAGE SN74AHC86 . . . D, DB, DGV, N, NS,
OR PW PACKAGE
(TOP VIEW)
1A
1
1B
2
1Y
3
2A
4
2B
5
2Y
6
GND
7
14 13 12 11 10
V
CC
4B 4A 4Y 3B 3A
9
3Y
8
SN74AHC86 . . . RGY PACKAGE
1B 1Y 2A 2B 2Y
(TOP VIEW)
1A
114 2 3 4 5 6
78
V
CC
13 12 11 10
4B 4A 4Y 3B
9
3A
3Y
GND
SN54AHC86 . . . FK PACKAGE
1Y
NC
2A
NC
2B
NC – No internal connection
(TOP VIEW)
1B1ANC
3212019
4 5 6 7 8
910111213
2Y
NC
GND
CC
V
3Y
description/ordering information
The ’AHC86 devices are quadruple 2-input exclusive-OR gates. These devices perform the Boolean function Y = A B or Y = A
A common application is as a true/complement element. If one of the inputs is low, the other input is reproduced in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the output.
–40°C to 85°C
–55°C to 125°C
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
B + AB in positive logic.
T
A
QFN – RGY Tape and reel SN74AHC86RGYR HA86 PDIP – N Tube SN74AHC86N SN74AHC86N
SOP – NS Tape and reel SN74AHC86NSR AHC86 SSOP – DB Tape and reel SN74AHC86DBR HA86
TVSOP – DGV Tape and reel SN74AHC86DGVR HA86 CDIP – J Tube SNJ54AHC86J SNJ54AHC86J CFP – W Tube SNJ54AHC86W SNJ54AHC86W LCCC – FK Tube SNJ54AHC86FK SNJ54AHC86FK
ORDERING INFORMATION
PACKAGE
Tube SN74AHC86D Tape and reel SN74AHC86DR
Tube SN74AHC86PW Tape and reel SN74AHC86PWR
ORDERABLE
PART NUMBER
TOP-SIDE MARKING
4B
18 17 16 15 14
3A
4A NC 4Y NC 3B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
1
SN54AHC86, SN74AHC86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCLS249I – OCTOBER 1995 – REVISED JULY 2003
FUNCTION TABLE
(each gate)
INPUTS
A B
L L L
L HH H LH H H L
exclusive-OR logic
An exclusive-OR gate has many applications, some of which can be represented better by alternative logic symbols.
EXCLUSIVE OR
= 1
These are five equivalent exclusive-OR symbols valid for an SN74AHC86 gate in positive logic; negation may be shown at any two ports.
OUTPUT
Y
LOGIC-IDENTITY ELEMENT EVEN-PARITY ELEMENT ODD-PARITY ELEMENT
= 2k 2k + 1
The output is active (low) if all inputs stand at the same logic level (i.e., A = B).
The output is active (low) if an even number of inputs (i.e., 0 or 2) are active.
The output is active (high) if an odd number of inputs (i.e., only 1 of the 2) are active.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V Input voltage range, V Output voltage range, V Input clamp current, I Output clamp current, I Continuous output current, I Continuous current through V Package thermal impedance, θ
Storage temperature range, T
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. The package thermal impedance is calculated in accordance with JESD 51-5.
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(V
< 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(V
OK
< 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(V
= 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
O
or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
(see Note 2): DB package 96°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): DGV package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): NS package 76°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): RGY package 47°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
UNIT
mA
mA
t/v
Input transition rise or fall rate
ns/V
PARAMETER
TEST CONDITIONS
V
UNIT
OH
OL
SN54AHC86, SN74AHC86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCLS249I – OCTOBER 1995 – REVISED JULY 2003
recommended operating conditions (see Note 4)
SN54AHC86 SN74AHC86
MIN MAX MIN MAX
V
V
V
V V
I
OH
I
OL
T
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 2 5.5 2 5.5 V
CC
VCC = 2 V 1.5 1.5
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 5.5 0 5.5 V
I
Output voltage 0 V
O
High-level output current
Low-level output current
p
Operating free-air temperature –55 125 –40 85 °C
A
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
VCC = 3 V VCC = 5.5 V 3.85 3.85 VCC = 2 V 0.5 0.5 VCC = 3 V VCC = 5.5 V 1.65 1.65
VCC = 2 V –50 –50 VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V –8 –8 VCC = 2 V 50 50 VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V 8 8 VCC = 3.3 V ± 0.3 V 100 100 VCC = 5 V ± 0.5 V 20 20
2.1 2.1
0.9 0.9
CC
–4 –4
4 4
0 V
CC
V
V
V
m
A
m
A
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
CC
2 V 1.9 2 1.9 1.9
IOH = –50 mA
V
OH
IOH = –4 mA IOH = –8 mA
IOL = 50 mA
V
OL
IOL = 4 mA IOL = 8 mA
I
I
I
CC
C
i
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
VI = 5.5 V or GND 0 V to 5.5 V ±0.1 ±1* ±1 VI = VCC or GND, IO = 0 5.5 V 2 20 20 VI = VCC or GND 5 V 4 10 10 pF
3 V 2.9 3 2.9 2.9
4.5 V 4.4 4.5 4.4 4.4 3 V 2.58 2.48 2.48
4.5 V 3.94 3.8 3.8 2 V 0.1 0.1 0.1 3 V 0.1 0.1 0.1
4.5 V 0.1 0.1 0.1 3 V 0.36 0.5 0.44
4.5 V 0.36 0.5 0.44
TA = 25°C SN54AHC86 SN74AHC86
MIN TYP MAX MIN MAX MIN MAX
V
V
m
A
m
A
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3
SN54AHC86, SN74AHC86
PARAMETER
UNIT
A or B
Y
C
15 pF
ns
A or B
Y
C
50 pF
ns
PARAMETER
UNIT
A or B
Y
C
15 pF
ns
A or B
Y
C
50 pF
ns
PARAMETER
UNIT
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCLS249I – OCTOBER 1995 – REVISED JULY 2003
switching characteristics over recommended operating free-air temperature range, V
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
t
PLH
t
PHL
t
PLH
t
PHL
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
p
=
L
p
=
L
switching characteristics over recommended operating free-air temperature range, V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
t
PLH
t
PHL
t
PLH
t
PHL
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
p
=
L
p
=
L
TA = 25°C SN54AHC86 SN74AHC86
MIN TYP MAX MIN MAX MIN MAX
7* 11* 1* 13* 1 13 7* 11* 1* 13* 1 13
9.5 14.5 1 16.5 1 16.5
9.5 14.5 1 16.5 1 16.5
TA = 25°C SN54AHC86 SN74AHC86
MIN TYP MAX MIN MAX MIN MAX
4.8* 6.8* 1* 8* 1 8
4.8* 6.8* 1* 8* 1 8
6.3 8.8 1 10 1 10
6.3 8.8 1 10 1 10
noise characteristics, V
V
OL(P)
V
OL(V)
V
OH(V)
V
IH(D)
V
IL(D)
NOTE 5: Characteristics are for surface-mount packages only.
Quiet output, maximum dynamic V Quiet output, minimum dynamic V Quiet output, minimum dynamic V High-level dynamic input voltage 3.5 V Low-level dynamic input voltage 1.5 V
operating characteristics, V
C
Power dissipation capacitance No load, f = 1 MHz 18 pF
pd
= 5 V, CL = 50 pF, TA = 25°C (see Note 5)
CC
OL OL OH
= 5 V, TA = 25°C
CC
PARAMETER TEST CONDITIONS TYP UNIT
SN74AHC86
MIN TYP MAX
0.3 0.8 V
–0.3 –0.8 V
4.4 V
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
From Output
Under Test
(see Note A)
SN54AHC86, SN74AHC86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCLS249I – OCTOBER 1995 – REVISED JULY 2003
PARAMETER MEASUREMENT INFORMATION
V
Test Point
C
L
From Output
Under Test
(see Note A)
C
L
RL = 1 k
S1
CC
Open
GND
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open Drain
Open
V
CC
GND V
CC
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Input
Input
t
PLH
In-Phase
Output
t
PHL
Out-of-Phase
Output
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
t
w
50% V
CC
VOLTAGE WAVEFORMS
PULSE DURATION
50% V
CC
50% V
50% V
VOLTAGE WAVEFORMS
50% V
CC
CC
3-STATE AND OPEN-DRAIN OUTPUTS
50% V
LOAD CIRCUIT FOR
V
CC
CC
0 V
V
CC
CC
t
PHL
50% V
t
PLH
50% V
CC
CC
0 V
V
V
V
V
OH
OL
OH
OL
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
50% V
t
su
50% V
CC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
50% V
CC
t
PZL
50% V
50% V
CC
CC
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
CC
t
50% V
50% V
h
CC
CC
t
PLZ
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
V
CC
0 V
V
CC
0 V
V
CC
0 V
V
V
OL
V
OH
0 V
CC
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 Ω, tr 3 ns, tf 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
5
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2007, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
PACKAGING INFORMATION
Orderable Device Status
5962-9681601Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type 5962-9681601QCA ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type 5962-9681601QDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type
SN74AHC86D ACTIVE SOIC D 14 50 Green (RoHS &
SN74AHC86DBLE OBSOLETE SSOP DB 14 TBD Call TI Call TI
SN74AHC86DBR ACTIVE SSOP DB 14 2000 Green(RoHS &
SN74AHC86DBRE4 ACTIVE SSOP DB 14 2000 Green (RoHS &
SN74AHC86DBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS &
SN74AHC86DE4 ACTIVE SOIC D 14 50 Green (RoHS &
SN74AHC86DG4 ACTIVE SOIC D 14 50 Green (RoHS &
SN74AHC86DGVR ACTIVE TVSOP DGV 14 2000 Green (RoHS &
SN74AHC86DGVRE4 ACTIVE TVSOP DGV 14 2000 Green (RoHS &
SN74AHC86DGVRG4 ACTIVE TVSOP DGV 14 2000 Green(RoHS &
SN74AHC86DR ACTIVE SOIC D 14 2500 Green (RoHS &
SN74AHC86DRE4 ACTIVE SOIC D 14 2500 Green (RoHS &
SN74AHC86DRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
SN74AHC86N ACTIVE PDIP N 14 25 Pb-Free
SN74AHC86NE4 ACTIVE PDIP N 14 25 Pb-Free
SN74AHC86NSR ACTIVE SO NS 14 2000 Green (RoHS &
SN74AHC86NSRE4 ACTIVE SO NS 14 2000 Green (RoHS &
SN74AHC86NSRG4 ACTIVE SO NS 14 2000 Green (RoHS &
SN74AHC86PW ACTIVE TSSOP PW 14 90 Green (RoHS &
SN74AHC86PWE4 ACTIVE TSSOP PW 14 90 Green (RoHS &
SN74AHC86PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS &
SN74AHC86PWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI
SN74AHC86PWR ACTIVE TSSOP PW 14 2000 Green (RoHS &
SN74AHC86PWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS &
(1)
Package
Type
Package Drawing
Pins Package
Qty
Eco Plan
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
(RoHS)
(RoHS)
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
9-Oct-2007
(3)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device Status
(1)
Package
Type
Package Drawing
Pins Package
Qty
Eco Plan
(2)
SN74AHC86PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS &
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-1-260C-UNLIM
9-Oct-2007
(3)
no Sb/Br)
SN74AHC86RGYR ACTIVE QFN RGY 14 1000 Green (RoHS &
CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SN74AHC86RGYRG4 ACTIVE QFN RGY 14 1000 Green(RoHS &
CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SNJ54AHC86FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
SNJ54AHC86J ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type
SNJ54AHC86W ACTIVE CFP W 14 1 TBD A42 N/ A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
TAPE AND REEL INFORMATION
19-Mar-2008
*All dimensions are nominal
Device Package
SN74AHC86DBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
SN74AHC86DGVR TVSOP DGV 14 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1
SN74AHC86DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74AHC86NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74AHC86PWR TSSOP PW 14 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1
SN74AHC86RGYR QFN RGY 14 1000 180.0 12.4 3.85 3.85 1.35 8.0 12.0 Q1
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm)W(mm)
Pin1
Quadrant
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74AHC86DBR SSOP DB 14 2000 346.0 346.0 33.0
SN74AHC86DGVR TVSOP DGV 14 2000 346.0 346.0 29.0
SN74AHC86DR SOIC D 14 2500 346.0 346.0 33.0
SN74AHC86NSR SO NS 14 2000 346.0 346.0 33.0
SN74AHC86PWR TSSOP PW 14 2000 346.0 346.0 29.0
SN74AHC86RGYR QFN RGY 14 1000 190.5 212.7 31.8
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,65
28
1
2,00 MAX
0,38 0,22
15
14
A
0,05 MIN
0,15
M
5,60 5,00
Seating Plane
8,20 7,40
0,10
0,25 0,09
0°ā8°
Gage Plane
0,25
0,95 0,55
PINS **
DIM
A MAX
A MIN
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150
14
6,50
6,50
5,905,90
2016
7,50
6,90
24
8,50
28
10,50
9,907,90
30
10,50
9,90
38
12,90
12,30
4040065 /E 12/01
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A SQ
B SQ
19
20
21
22
23
24
25
12826 27
12
1314151618 17
0.020 (0,51)
0.010 (0,25)
MIN
0.342 (8,69)
0.442
0.640
0.739
0.938
1.141
A
0.358 (9,09)
0.458
(11,63)
0.660
(16,76)
0.761
(19,32)(18,78)
0.962
(24,43)
1.165
(29,59)
NO. OF
TERMINALS
**
11
10
9
8
7
6
5
432
20
28
44
52
68
84
0.020 (0,51)
0.010 (0,25)
(11,23)
(16,26)
(23,83)
(28,99)
MINMAX
0.307 (7,80)
0.406
(10,31)
0.495
(12,58)
0.495
(12,58)
0.850 (21,6)
1.047 (26,6)
0.080 (2,03)
0.064 (1,63)
B
MAX
0.358
(9,09)
0.458
(11,63)
0.560
(14,22)
0.560
(14,22)
0.858 (21,8)
1.063 (27,0)
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
4040140/D 10/96
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65
1,20 MAX
14
0,30 0,19
8
4,50 4,30
PINS **
7
Seating Plane
0,15 0,05
8
1
A
DIM
6,60 6,20
14
0,10
M
0,10
0,15 NOM
0°–8°
2016
Gage Plane
24
0,25
0,75 0,50
28
A MAX
A MIN
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
4040064/F 01/97
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
24
112
A
0,23 0,13
13
0,07
4,50 4,30
M
6,60 6,20
0,16 NOM
Gage Plane
0,25
0°8°
0,75 0,50
1,20 MAX
PINS **
DIM
A MAX
A MIN
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
0,15 0,05
14
3,70
3,50
Seating Plane
3,50
20
5,10
4,90
0,08
5,103,70
4,90
382416
7,90
7,70
48
9,80
9,60
56
11,40
11,20
4073251/E 08/00
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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