TEXAS INSTRUMENTS SN54AHC374 Technical data

SOIC
DW
AHC374
40°C to 85°C
TSSOP
PW
HA374
D
D
3-State Outputs Drive Bus Lines Directly
D
Latch-Up Performance Exceeds 250 mA Per
CC
JESD 17
SN74AHC374 . . . DB, DGV, DW, N, NS, OR PW PACKAGE
SN54AHC374 ...J OR W PACKAGE
(TOP VIEW)
1
20 19 18 17 16 15 14 13 12 11
V
CC
8Q 8D 7D 7Q 6Q 6D 5D 5Q CLK
OE
1Q 1D 2D 2Q 3Q 3D 4D 4Q
GND
2 3 4 5 6 7 8 9 10
SN54AHC374, SN74AHC374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS240I – OCTOBER 1995 – REVISED JUL Y 2003
D
ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101)
SN54AHC374 . . . FK PACKAGE
2D 2Q 3Q 3D 4D
(TOP VIEW)
1D1QOE
3 2 1 20 19
4 5 6 7 8
9 10 11 12 13
4Q
CLK
GND
V
CC
5Q
8Q
18 17 16 15 14
5D
8D 7D 7Q 6Q 6D
description/ordering information
The ’AHC374 devices are octal edge-triggered D-type flip-flops that feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels of the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly . The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components.
ORDERING INFORMA TION
T
A
PDIP – N Tube SN74AHC374N SN74AHC374N
–55°C to 125°C
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
SOP – NS Tape and reel SN74AHC374NSR AHC374 SSOP – DB Tape and reel SN74AHC374DBR HA374
TVSOP – DGV Tape and reel SN74AHC374DGVR HA374 CDIP – J Tube SNJ54AHC374J SNJ54AHC374J CFP – W Tube SNJ54AHC374W SNJ54AHC374W LCCC – FK Tube SNJ54AHC374FK SNJ54AHC374FK
PACKAGE
Tube SN74AHC374DW Tape and reel SN74AHC374DWR
Tube SN74AHC374PW Tape and reel SN74AHC374PWR
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
1
SN54AHC374, SN74AHC374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SCLS240I – OCTOBER 1995 – REVISED JULY 2003
description/ordering information (continued)
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
T o ensure the high-impedance state during power up or power down, OE
should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
(each flip-flop)
INPUTS
OE CLK D
L H H L LL L H or L X Q
H X X Z
OUTPUT
Q
0
logic diagram (positive logic)
1
OE
11
CLK
1D
3
C1
1D
2
1Q
through a pullup
CC
To Seven Other Channels
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
UNIT
mA
mA
t/∆v
Input transition rise or fall rate
ns/V
SN54AHC374, SN74AHC374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS240I – OCTOBER 1995 – REVISED JULY 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V Input voltage range, V Output voltage range, V Input clamp current, I Output clamp current, I Continuous output current, I Continuous current through V Package thermal impedance, θ
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
(see Note 1) –0.5 V to V
O
(V
< 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(V
OK
< 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(V
= 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
O
or GND ±75 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 2): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 92°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 83°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 3)
SN54AHC374 SN74AHC374
MIN MAX MIN MAX
V
V
V
V V
I
OH
I
OL
T
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 2 5.5 2 5.5 V
CC
VCC = 2 V 1.5 1.5
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 5.5 0 5.5 V
I
Output voltage 0 V
O
High-level output current
Low-level output current
p
Operating free-air temperature –55 125 –40 85 °C
A
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
VCC = 3 V VCC = 5.5 V 3.85 3.85 VCC = 2 V 0.5 0.5 VCC = 3 V VCC = 5.5 V 1.65 1.65
VCC = 2 V –50 –50 VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V –8 –8 VCC = 2 V 50 50 VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V 8 8 VCC = 3.3 V ± 0.3 V 100 100 VCC = 5 V ± 0.5 V 20 20
2.1 2.1
0.9 0.9
CC
–4 –4
4 4
0 V
CC
V
V
V
m
A
m
A
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3
SN54AHC374, SN74AHC374
PARAMETER
TEST CONDITIONS
V
UNIT
OH
OL
UNIT
UNIT
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SCLS240I – OCTOBER 1995 – REVISED JULY 2003
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
CC
2 V 1.9 2 1.9 1.9
IOH = –50 mA
V
OH
IOH = –4 mA IOH = –8 mA
IOL = 50 mA
V
OL
IOL = 4 mA IOL = 8 mA
I
I
I
OZ
I
CC
C
i
C
o
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
VI = 5.5 V or GND 0 V to 5.5 V ±0.1 ±1* ±1 VO = VCC or GND 5.5 V ±0.25 ±2.5 ±2.5 VI = VCC or GND, IO = 0 5.5 V 4 40 40 VI = VCC or GND 5 V 4 10 10 pF VO = VCC or GND 5 V 6 pF
3 V 2.9 3 2.9 2.9
4.5 V 4.4 4.5 4.4 4.4 3 V 2.58 2.48 2.48
4.5 V 3.94 3.8 3.8 2 V 0.1 0.1 0.1 3 V 0.1 0.1 0.1
4.5 V 0.1 0.1 0.1 3 V 0.36 0.5 0.44
4.5 V 0.36 0.5 0.44
TA = 25°C SN54AHC374 SN74AHC374
MIN TYP MAX MIN MAX MIN MAX
V
V
m
A
m
A
m
A
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
TA = 25°C SN54AHC374 SN74AHC374 MIN MAX MIN MAX MIN MAX
t
Pulse duration, CLK high or low 5 5.5 5.5 ns
w
t
Setup time, data before CLK
su
t
Hold time, data after CLK 2 2 2 ns
h
4.5 4 4 ns
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25°C SN54AHC374 SN74AHC374 MIN MAX MIN MAX MIN MAX
t
Pulse duration, CLK high or low 5 5 5 ns
w
t
Setup time, data before CLK
su
t
Hold time, data after CLK 2 2 2 ns
h
3 3 3 ns
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER
UNIT
f
MHz
CLK
Q
C
15 pF
ns
OE
Q
C
15 pF
ns
OE
Q
C
15 pF
ns
CLK
Q
C
50 pF
ns
OE
Q
C
50 pF
ns
OE
Q
C
50 pF
ns
PARAMETER
UNIT
f
MHz
CLK
Q
C
15 pF
ns
OE
Q
C
15 pF
ns
OE
Q
C
15 pF
ns
CLK
Q
C
50 pF
ns
OE
Q
C
50 pF
ns
OE
Q
C
50 pF
ns
SN54AHC374, SN74AHC374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS240I – OCTOBER 1995 – REVISED JULY 2003
switching characteristics over recommended operating free-air temperature range, V
= 3.3 V ±0.3 V (unless otherwise noted) (see Figure 1)
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
max
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
sk(o)
On products compliant to MIL-PRF-38535, this parameter is not production tested.
∗∗
On products compliant to MIL-PRF-38535, this parameter does not apply.
CL = 15 pF 80* 130* 70* 70 CL = 50 pF 55 85 50 50
p
=
L
p
=
L
p
=
L
p
=
L
p
=
L
p
=
L
CL = 50 pF 1.5** 1.5 ns
TA = 25°C SN54AHC374 SN74AHC374
MIN TYP MAX MIN MAX MIN MAX
8.1* 12.7* 1* 15* 1 15
8.1* 12.7* 1* 15* 1 15
7.1* 11* 1* 13* 1 13
7.1* 11* 1* 13* 1 13
7.5* 10.5* 1* 12.5* 1 12.5
7.5* 10.5* 1* 12.5* 1 12.5
10.6 16.2 1 18.5 1 18.5
10.6 16.2 1 18.5 1 18.5
9.6 14.5 1 16.5 1 16.5
9.6 14.5 1 16.5 1 16.5
10.2 14 1 16 1 16
10.2 14 1 16 1 16
switching characteristics over recommended operating free-air temperature range, V
= 5 V ±0.5 V (unless otherwise noted) (see Figure 1)
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
max
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
sk(o)
On products compliant to MIL-PRF-38535, this parameter is not production tested.
∗∗
On products compliant to MIL-PRF-38535, this parameter does not apply.
CL = 15 pF 130* 185* 110* 110 CL = 50 pF 85 120 75 75
p
=
L
p
=
L
p
=
L
p
=
L
p
=
L
p
=
L
CL = 50 pF 1** 1 ns
TA = 25°C SN54AHC374 SN74AHC374
MIN TYP MAX MIN MAX MIN MAX
5.4* 8.1* 1* 9.5* 1 9.5
5.4* 8.1* 1* 9.5* 1 9.5
5.1* 7.6* 1* 9* 1 9
5.1* 7.6* 1* 9* 1 9
4.6* 6.8* 1* 8* 1 8
4.6* 6.8* 1* 8* 1 8
6.9 10.1 1 11.5 1 11.5
6.9 10.1 1 11.5 1 11.5
6.6 9.6 1 11 1 11
6.6 9.6 1 11 1 11
6.1 8.8 1 10 1 10
6.1 8.8 1 10 1 10
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
5
SN54AHC374, SN74AHC374
PARAMETER
UNIT
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SCLS240I – OCTOBER 1995 – REVISED JULY 2003
noise characteristics, V
V
OL(P)
V
OL(V)
V
OH(V)
V
IH(D)
V
IL(D)
NOTE 4: Characteristics are for surface-mount packages only.
Quiet output, maximum dynamic V Quiet output, minimum dynamic V Quiet output, minimum dynamic V High-level dynamic input voltage 3.5 V Low-level dynamic input voltage 1.5 V
operating characteristics, V
C
Power dissipation capacitance No load, f = 1 MHz 32 pF
pd
= 5 V, CL = 50 pF, TA = 25°C (see Note 4)
CC
OL OL OH
= 5 V, TA = 25°C
CC
PARAMETER TEST CONDITIONS TYP UNIT
SN74AHC374
MIN TYP MAX
0.5 1 V
–0.5 –0.8 V
4 V
6
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
From Output
Under Test
(see Note A)
SN54AHC374, SN74AHC374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS240I – OCTOBER 1995 – REVISED JULY 2003
PARAMETER MEASUREMENT INFORMATION
V
Test Point
C
L
From Output
Under Test
(see Note A)
C
L
RL = 1 k
S1
CC
Open
GND
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open Drain
Open
V
CC
GND V
CC
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Input
Input
t
PLH
In-Phase
Output
t
PHL
Out-of-Phase
Output
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
t
w
50% V
CC
VOLTAGE WAVEFORMS
PULSE DURATION
50% V
CC
50% V
50% V
VOLTAGE WAVEFORMS
50% V
CC
CC
3-STATE AND OPEN-DRAIN OUTPUTS
50% V
LOAD CIRCUIT FOR
V
CC
CC
0 V
V
CC
CC
t
PHL
50% V
t
PLH
50% V
CC
CC
0 V
V
V
V
V
OH
OL
OH
OL
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
50% V
t
su
50% V
CC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
50% V
CC
t
PZL
50% V
50% V
CC
CC
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
CC
t
50% V
50% V
h
CC
CC
t
PLZ
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
V
CC
0 V
V
CC
0 V
V
CC
0 V
V
V
OL
V
OH
0 V
CC
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 Ω, tr 3 ns, tf 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
7
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