TEXAS INSTRUMENTS SN54AHC174 Technical data

SOIC

AHC174

SN54AHC174, SN74AHC174

HEX D-TYPE FLIP-FLOPS

WITH CLEAR

SCLS425F – JUNE 1998 – REVISED FEBRUARY 2002

Operating Range 2-V to 5.5-V V

Contain Six Flip-Flops With Single-Rail

Outputs

Applications Include: – Buffer/Storage Registers – Shift Registers – Pattern Generators

Latch-Up Performance Exceeds 250 mA Per JESD 17

ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101)

description

The ’AHC174 devices are positive-edge-triggered D-type flip-flops with a direct clear (CLR are designed for 2-V to 5.5-V V

Information at the data (D) inputs that meets the setup time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low level, the D input has no effect at the output.

operation.

) input and

SN74AHC174 . . . D, DB, DGV, N, NS, OR PW PACKAGE

SN54AHC174 ...J OR W PACKAGE

(TOP VIEW)

16 15 14 13 12 11 10

CLK

6Q 6D 5D 5Q 4D 4Q CLK

18 17 16 15 14

6D 5D NC 5Q 4D

CLR

GND

SN54AHC174 . . . FK PACKAGE

1D 2D

2Q 3D

(TOP VIEW)

CLR

3212019

4 5 6 7 8

910111213

GND

NC – No internal connection

PDIP – N Tube SN74AHC174N SN74AHC174N

–

–40°C to 85°C

–55°C to 125°C

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

SOP – NS Tube SN74AHC174NSR AHC174 SSOP – DB Tape and reel SN74AHC174DBR HA174 TSSOP – PW Tape and reel SN74AHC174PWR HA174 TVSOP – DGV Tape and reel SN74AHC174DGVR HA174 CDIP – J Tube SNJ54AHC174J SNJ54AHC174J CFP – W Tube SNJ54AHC174W SNJ54AHC174W LCCC – FK Tube SNJ54AHC174FK SNJ54AHC174FK

ORDERING INFORMA TION

PACKAGE

†

Tube SN74AHC174D Tape and reel SN74AHC174DR

ORDERABLE

PART NUMBER

TOP-SIDE MARKING

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SN54AHC174, SN74AHC174 HEX D-TYPE FLIP-FLOPS WITH CLEAR

SCLS425F – JUNE 1998 – REVISED FEBRUARY 2002

logic diagram (positive logic)

CLR

CLK

FUNCTION TABLE

(each flip-flop)

INPUTS

CLR CLK D

L X X L H ↑ HH H ↑ LL H L X Q

OUTPUT

To Five Other Channels

Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, and W packages.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V Input voltage range, V Output voltage range, V Input clamp current, I Output clamp current, I Continuous output current, I Continuous current through V Package thermal impedance, θ

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(VI < 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(VO < 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 2): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DB package 82°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DGV package 120°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NS package 64°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 108°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

†

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UNIT

Dt/DvInput transition rise or fall rate

ns/V

PARAMETER

TEST CONDITIONS

UNIT

SN54AHC174, SN74AHC174

HEX D-TYPE FLIP-FLOPS

WITH CLEAR

SCLS425F – JUNE 1998 – REVISED FEBRUARY 2002

recommended operating conditions (see Note 3)

SN54AHC174 SN74AHC174

MIN MAX MIN MAX

V V

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Supply voltage 2 5.5 2 5.5 V

VCC = 2 V 1.5 1.5

High-level input voltage

Low-level input voltage

Input voltage 0 5.5 0 5.5 V

Output voltage 0 V

High-level output current

Low-level output current

Operating free-air temperature –55 125 –40 85 °C

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

VCC = 3 V VCC = 5.5 V 3.85 3.85 VCC = 2 V 0.5 0.5 VCC = 3 V VCC = 5.5 V 1.65 1.65

VCC = 2 V –50 –50 VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V –8 –8 VCC = 2 V 50 50 VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V 8 8 VCC = 3.3 V ± 0.3 V 100 100 VCC = 5 V ± 0.5 V 20 20

2.1 2.1

0.9 0.9

–4 –4

4 4

0 V

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

2 V 1.9 2 1.9 1.9

IOH = –50 mA

IOH = –4 mA IOH = –8 mA

IOL = 50 mA

IOL = 4 mA IOL = 8 mA

* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.

VI = 5.5 V or GND 0 V to 5.5 V ± 0.1 ± 1* ± 1 VI = VCC or GND, IO = 0 5.5 V 4 40 40 VI = VCC or GND 5 V 1.7 10 10 pF

3 V 2.9 3 2.9 2.9

4.5 V 4.4 4.5 4.4 4.4 3 V 2.58 2.48 2.48

4.5 V 3.94 3.8 3.8 2 V 0.1 0.1 0.1 3 V 0.1 0.1 0.1

4.5 V 0.1 0.1 0.1 3 V 0.36 0.5 0.44

4.5 V 0.36 0.5 0.44

TA = 25°C SN54AHC174 SN74AHC174

MIN TYP MAX MIN MAX MIN MAX

PRODUCT PREVIEW information concerns products in the formative or

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other

design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to

specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

change or discontinue these products without notice.

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SN54AHC174, SN74AHC174

UNIT

twPulse duration

tsuSetup time before CLK↑

UNIT

twPulse duration

tsuSetup time before CLK↑

PARAMETER

UNIT

MHz

CLK

Any Q

15 pF

CLK

Any Q

50 pF

HEX D-TYPE FLIP-FLOPS WITH CLEAR

SCLS425F – JUNE 1998 – REVISED FEBRUARY 2002

timing requirements over recommended operating free-air temperature range, V

(unless otherwise noted)

TA = 25°C SN54AHC174 SN74AHC174 MIN MAX MIN MAX MIN MAX

CLR low 5 5 5 CLK high or low 5 5 5

Hold time, data after CLK↑ 0 0 0 ns

timing requirements over recommended operating free-air temperature range, V

Data 5 6 6 CLR inactive 3 3 3

(unless otherwise noted)

TA = 25°C SN54AHC174 SN74AHC174 MIN MAX MIN MAX MIN MAX

CLR low 5 5 5 CLK high or low 5 5 5

Hold time, data after CLK↑ 0.5 0.5 0.5 ns

Data 4.5 4.5 4.5 CLR inactive 2.5 2.5 2.5

switching characteristics over recommended operating free-air temperature range, V

= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)

FROM TO LOAD

(INPUT) (OUTPUT) CAPACITANCE

max

PHL

PLH

PHL

PLH

PHL

sk(o)

* On products compliant to MIL-PRF-38535, this parameter is not production tested. ** On products compliant to MIL-PRF-38535, this parameter does not apply.

CLR Any Q CL = 15 pF 4.5* 11.4* 1* 13.5* 1 13.5 ns

CLR Any Q CL = 50 pF 6 14.9 1 17 1 17 ns

CL = 15 pF 95* 170* 80* 80 CL = 50 pF 55 130 50 50

CL = 50 pF 1.5** 1.5 ns

TA = 25°C SN54AHC174 SN74AHC174

MIN TYP MAX MIN MAX MIN MAX

5.8* 11* 1* 13* 1 13

7.5 14.5 1 16.5 1 16.5

= 3.3 V ± 0.3 V

= 5 V ± 0.5 V

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER

UNIT

MHz

CLK

Any Q

15 pF

CLK

Any Q

50 pF

SN54AHC174, SN74AHC174

HEX D-TYPE FLIP-FLOPS

SCLS425F – JUNE 1998 – REVISED FEBRUARY 2002

switching characteristics over recommended operating free-air temperature range, V

= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)

FROM TO LOAD

(INPUT) (OUTPUT) CAPACITANCE

max

PHL

PLH

PHL

PLH

PHL

sk(o)

* On products compliant to MIL-PRF-38535, this parameter is not production tested. ** On products compliant to MIL-PRF-38535, this parameter does not apply.

CLR Any Q CL = 15 pF 3* 7.6* 1* 9* 1 9 ns

CLR Any Q CL = 50 pF 4.2 9.6 1 11 1 11 ns

CL = 15 pF 130* 240* 110* 110 CL = 50 pF 90 180 80 80

CL = 50 pF 1** 1 ns

operating characteristics, TA = 25°C

PARAMETER TEST CONDITIONS TYP UNIT

Power dissipation capacitance No load, f = 1 MHz 15.2 pF

TA = 25°C SN54AHC174 SN74AHC174

MIN TYP MAX MIN MAX MIN MAX

4.1* 7.2* 1* 8.5* 1 8.5

5.5 9.2 1 10.5 1 10.5

WITH CLEAR

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54AHC174, SN74AHC174 HEX D-TYPE FLIP-FLOPS WITH CLEAR

SCLS425F – JUNE 1998 – REVISED FEBRUARY 2002

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

(see Note A)

Test Point

From Output

Under Test

(see Note A)

RL = 1 kΩ

Open

GND

TEST S1

PLH/tPHL

PLZ/tPZL

PHZ/tPZH

Open Drain

Open

GND

LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS

Input

VOLTAGE WAVEFORMS

Input

PLH

In-Phase

Output

PHL

Out-of-Phase

Output

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

50% V

PULSE DURATION

50% V

3-STATE AND OPEN-DRAIN OUTPUTS

50% V

LOAD CIRCUIT FOR

0 V

PHL

50% V

PLH

50% V

0 V

Timing Input

Waveform 1

(see Note B)

Waveform 2

(see Note B)

Data Input

Output

Control

Output

S1 at V

Output

S1 at GND

50% V

PLZ

VOL + 0.3 V

PHZ

VOH – 0.3 V

50% V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

50% V

PZL

50% V

PZH

50% V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

0 V

≈V

≈0 V

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

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