TEXAS INSTRUMENTS SN54AHC132 Technical data
SOIC
D
AHC132
40°C to 85°C
查询SN54AHC132供应商
D
Operating Range 2-V to 5.5-V V
D
Operation From Very Slow Input
Transitions
D
T emperature-Compensated Threshold
Levels
D
High Noise Immunity
SN54AHC132 ...J OR W PACKAGE
SN74AHC132 . . . D, DB, DGV, N, NS,
OR PW PACKAGE
(TOP VIEW)
1A
1
1B
2
1Y
3
2A
4
2B
5
6
2Y
GND
7
14
13
12
11
10
V
4B
4A
4Y
3B
9
3A
8
3Y
CC
CC
D
D
D
SN74AHC132 . . . RGY PACKAGE
1B
1Y
2A
2B
2Y
(TOP VIEW)
1A
114
2
3
4
5
6
78
GND
CC
V
3Y
SN54AHC132, SN74AHC132
QUADRUPLE POSITIVE-NAND GATES
WITH SCHMITT-TRIGGER INPUTS
SCLS365G – MAY 1997 – REVISED SEPTEMBER 2002
Same Pinouts as ’AHC00
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
13
12
11
10
SN54AHC132 . . . FK PACKAGE
4B
4A
4Y
3B
9
3A
1Y
NC
2A
NC
2B
NC – No internal connection
(TOP VIEW)
1B1ANC
3212019
4
5
6
7
8
910111213
2Y
NC
GND
CC
V
3Y
4B
18
17
16
15
14
3A
4A
NC
4Y
NC
3B
description/ordering information
The ’AHC132 devices are quadruple positive-NAND gates designed for 2-V to 5.5-V VCC operation.
These devices perform the Boolean function Y = A
ORDERING INFORMA TION
T
A
QFN – RGY Tape and reel SN74AHC132RGYR HA132
PDIP – N Tube SN74AHC132N SN74AHC132N
°
–
–55°C to 125°C
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
°
SOP – NS Tape and reel SN74AHC132NSR AHC132
SSOP – DB Tape and reel SN74AHC132DBR HA132
TSSOP – PW Tape and reel SN74AHC132PWR HA132
TVSOP – DGV Tape and reel SN74AHC132DGVR HA132
CDIP – J Tube SNJ54AHC132J SNJ54AHC132J
CFP – W Tube SNJ54AHC132W SNJ54AHC132W
LCCC – FK Tube SNJ54AHC132FK SNJ54AHC132FK
PACKAGE
–
†
Tube SN74AHC132D
Tape and reel SN74AHC132DR
• B or Y = A + B in positive logic.
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2002, Texas Instruments Incorporated
1
SN54AHC132, SN74AHC132
QUADRUPLE POSITIVE-NAND GATES
WITH SCHMITT-TRIGGER INPUTS
SCLS365G – MAY 1997 – REVISED SEPTEMBER 2002
description/ordering information (continued)
Each circuit functions as a NAND gate, but because of the Schmitt action, it has different input threshold levels
for positive- and negative-going signals.
These circuits are temperature compensated and can be triggered from the slowest of input ramps and still give
clean jitter-free output signals.
FUNCTION TABLE
(each gate)
INPUTS
A B
H H L
L XH
X L H
logic diagram, each gate (positive logic)
A
OUTPUT
Y
Y
B
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
Output voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. The package thermal impedance is calculated in accordance with JESD 51-5.
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
(see Note 1) –0.5 V to V
O
(V
< 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(V
OK
< 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(V
= 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
O
or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 2): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
(see Note 2): DB package 96°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): DGV package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): NS package 76°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): RGY package 47°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
mA
mA
PARAMETER
TEST CONDITIONS
V
UNIT
V
T+
V
T
Hysteresis (V
T
V
T
)
SN54AHC132, SN74AHC132
QUADRUPLE POSITIVE-NAND GATES
WITH SCHMITT-TRIGGER INPUTS
SCLS365G – MAY 1997 – REVISED SEPTEMBER 2002
recommended operating conditions (see Note 4)
SN54AHC132 SN74AHC132
MIN MAX MIN MAX
V
V
V
I
OH
I
OL
T
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
input threshold voltage
input threshold voltage
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
Supply voltage 2 5.5 2 5.5 V
CC
Input voltage 0 5.5 0 5.5 V
I
Output voltage 0 V
O
VCC = 2 V –50 –50
High-level output current
Low-level output current
Operating free-air temperature –55 125 –40 85 °C
A
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Positive-going
–
Negative-going
∆V
T
–
–
+
V
OH
V
OL
I
I
I
CC
C
i
–
IOH = –50 mA
IOH = –4 mA 3 V 2.58 2.48 2.48
IOH = –8 mA 4.5 V 3.94 3.8 3.8
IOL = 50 mA
IOL = 4 mA 3 V 0.36 0.5 0.44
IOL = 8 mA 4.5 V 0.36 0.5 0.44
VI = 5.5 V or GND 0 V to 5.5 V ±0.1 ±1* ±1
VI = VCC or GND, IO = 0 5.5 V 2 20 20
VI = VCC or GND 5 V 1.9 10 10 pF
4.5 V 1.75 3.15 1.75 3.15 1.75 3.15
5.5 V 2.15 3.85 2.15 3.85 2.15 3.85
4.5 V 1.35 2.75 1.35 2.75 1.35 2.75
5.5 V 1.65 3.35 1.65 3.35 1.65 3.35
4.5 V 0.4 1.4 0.4 1.4 0.4 1.4
5.5 V 0.5 1.6 0.5 1.6 0.5 1.6
4.5 V 4.4 4.5 4.4 4.4
4.5 V 0.1 0.1 0.1
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V –8 –8
VCC = 2 V 50 50
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V 8 8
CC
3 V 1.2 2.2 1.2 2.2 1.2 2.2
3 V 0.9 1.9 0.9 1.9 0.9 1.9
3 V 0.3 1.2 0.3 1.2 0.3 1.2
2 V 1.9 2 1.9 1.9
3 V 2.9 3 2.9 2.9
2 V 0.1 0.1 0.1
3 V 0.1 0.1 0.1
TA = 25°C SN54AHC132 SN74AHC132
MIN TYP MAX MIN MAX MIN MAX
CC
–4 –4
4 4
0 V
CC
V
m
A
m
A
V
V
V
V
V
m
A
m
A
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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