TEXAS INSTRUMENTS SN54ACT574 Technical data

SOIC

DW

ACT574

40°C to 85°C

SN54ACT574, SN74ACT574

OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

WITH 3-STATE OUTPUTS

SCAS537D – OCTOBER 1995 – REVISED NOVEMBER 2002

D

4.5-V to 5.5-V VCC Operation

D

Inputs Accept Voltages to 5.5 V

D

Max tpd of 9 ns at 5 V

D

Inputs Are TTL-Voltage Compatible

description/ordering information

These 8-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. The devices
are particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.

The eight flip-flops of the ’ACT574 devices are
D-type edge-triggered flip-flops. On the positive
transition of the clock (CLK) input, the Q outputs
are set to the logic levels set up at the data (D)
inputs.

A buffered output-enable (OE
to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
the increased drive provide the capability to drive
bus lines in a bus-organized system without need
for interface or pullup components.

) input can be used

SN54ACT574 ...J OR W PACKAGE

SN74ACT574 . . . DB, DW, N, NS, OR PW PACKAGE

SN54ACT574 . . . FK PACKAGE

3D
4D
5D
6D
7D

(TOP VIEW)

1

OE

2

1D

3

2D

4

3D

5

4D

6

5D

7

6D

8

7D

9

8D

GND

10

(TOP VIEW)

2D1DOE

3212019

4
5
6
7
8

910111213

8D

GND

20
19
18
17
16
15
14
13
12
11

CLK

V

8Q

CC

V

CC

1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLK

1Q

18
17
16
15
14

7Q

2Q
3Q
4Q
5Q
6Q

OE

does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while

the outputs are in the high-impedance state.
T o ensure the high-impedance state during power up or power down, OE

should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

ORDERING INFORMA TION

T

A

PDIP – N Tube SN74ACT574N SN74ACT574N

–

–55°C to 125°C

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SOP – NS Tape and reel SN74ACT574NSR ACT574
SSOP – DB Tape and reel SN74ACT574DBR AD574
TSSOP – PW Tape and reel SN74ACT574PWR AD574
CDIP – J Tube SNJ54ACT574J SNJ54ACT574J
CFP – W Tube SNJ54ACT574W SNJ54ACT574W
LCCC – FK Tube SNJ54ACT574FK SNJ54ACT574FK

PACKAGE

–

†

Tube SN74ACT574DW
Tape and reel SN74ACT574DWR

ORDERABLE

PART NUMBER

TOP-SIDE
MARKING

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  2002, Texas Instruments Incorporated

1

SN54ACT574, SN74ACT574
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS

SCAS537D – OCTOBER 1995 – REVISED NOVEMBER 2002

FUNCTION TABLE

(each flip-flop)

INPUTS

OE CLK D

L ↑ H H
L ↑ LL
L H or L X Q

H X X Z

logic diagram (positive logic)

1

OE

11

CLK

OUTPUT

Q

0

1D

C1

2

To Seven Other Channels

1D

19

1Q

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Input voltage range, V
Output voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

(VI < 0 or VI > V

IK

(VO < 0 or VO > V

OK

(VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

or GND ±200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 2): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC)

±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC)

DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 83°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

†

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UNIT

PARAMETER

TEST CONDITIONS

V

UNIT

I

50 µA

V

I

24 mA

V

I

50 µA

V

I

24 mA

V

SN54ACT574, SN74ACT574

OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

WITH 3-STATE OUTPUTS

SCAS537D – OCTOBER 1995 – REVISED NOVEMBER 2002

recommended operating conditions (see Note 3)

SN54ACT574 SN74ACT574

MIN MAX MIN MAX

V
V
V
V
V
I

OH

I

OL

∆t/∆v Input transition rise or fall rate 8 8 ns/V
T

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

†

Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms.

‡

This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.

Supply voltage 4.5 5.5 4.5 5.5 V

CC

High-level input voltage 2 2 V

IH

Low-level input voltage 0.8 0.8 V

IL

Input voltage 0 V

I

Output voltage 0 V

O

High-level output current –24 –24 mA
Low-level output current 24 24 mA

Operating free-air temperature –55 125 –40 85 °C

A

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

TA = 25°C SN54ACT574 SN74ACT574

MIN TYP MAX MIN MAX MIN MAX

OH

OL

I

OZ

I

I

I

CC

∆ICC‡
C

i

CC

= –

OH

= –

OH

IOH = –50 mA
IOH = –75 mA

=

OL

=

OL

IOL = 50 mA
IOL = 75 mA
VO = VCC or GND 5.5 V ±0.25 ±5 ±2.5 µA
VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA
VI = VCC or GND, IO = 0 5.5 V 4 80 40 µA
One input at 3.4 V ,

Other inputs at GND or V
VI = VCC or GND 5 V 4.5 pF

†
†

†
†

CC

4.5 V 4.4 4.49 4.4 4.4

5.5 V 5.4 5.49 5.4 5.4

4.5 V 3.86 3.7 3.76

5.5 V 4.86 4.7 4.76

5.5 V 3.85

5.5 V 3.85

4.5 V 0.1 0.1 0.1

5.5 V 0.1 0.1 0.1

4.5 V 0.36 0.44 0.44

5.5 V 0.36 0.44 0.44

5.5 V 1.65

5.5 V 1.65

5.5 V 0.6 1.5 1.5 mA

CC
CC

0 V
0 V

CC
CC

V
V

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

SN54ACT574, SN74ACT574

UNIT

PARAMETER

UNIT

CLK

Q

ns

OE

Q

ns

OE

Q

ns

OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS

SCAS537D – OCTOBER 1995 – REVISED NOVEMBER 2002

timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)

TA = 25°C SN54ACT574 SN74ACT574
MIN MAX MIN MAX MIN MAX

f

clock

t

w

t

su

t

h

switching characteristics over recommended operating free-air temperature range,
V

CC

Clock frequency 100 70 85 MHz
Pulse duration, CLK high or low 3 5 4 ns
Setup time, data before CLK↑ 2.5 3.5 2.5 ns
Hold time, data after CLK↑ 1 2 1 ns

= 5 V ± 0.5V (unless otherwise noted) (see Figure 1)

TA = 25°C SN54ACT574 SN74ACT574

MIN TYP MAX MIN MAX MIN MAX

100 110 70 85 MHz

2.5 7 11 1.5 13.5 2 12
2 6.5 10 1.5 12.5 1.5 11
2 6.4 9.5 1.5 11 1.5 10
2 6 9 1.5 11 1.5 10
2 7 10.5 1.5 12 1.5 11.5
2 5.5 8.5 1.5 10 1.5 9

f

max

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

FROM TO

(INPUT) (OUTPUT)

operating characteristics, VCC = 5 V, TA = 25°C

PARAMETER TEST CONDITIONS TYP UNIT

C

Power dissipation capacitance CL = 50 pF, f = 1 MHz 40 pF

pd

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265