TEXAS INSTRUMENTS SN54ACT573 Technical data

SOIC

DW

ACT573

40°C to 85°C

SN54ACT573, SN74ACT573

OCTAL D-TYPE TRANSPARENT LATCHES

WITH 3-STATE OUTPUTS

SCAS538D – OCTOBER 1995 – REVISED OCTOBER 2002

D

4.5-V to 5.5-V VCC Operation

D

Inputs Accept Voltages to 5.5 V

D

Max tpd of 9.5 ns at 5 V

D

Inputs Are TTL-Voltage Compatible

description/ordering information

These 8-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. The devices
are particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.

The eight latches are D-type transparent latches.
When the latch-enable (LE) input is high, the Q
outputs follow the data (D) inputs. When LE is
taken low, the Q outputs are latched at the logic
levels set up at the D inputs.

A buffered output-enable (OE
to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
increased drive provide the capability to drive bus
lines in a bus-organized system without need for
interface or pullup components.

OE

does not affect the internal operations of the latches. Old data can be retained or new data can be entered

while the outputs are in the high-impedance state.

) input can be used

SN54ACT573 ...J OR W PACKAGE

SN74ACT573 . . . DB, DW, N, NS, OR PW P ACKAGE

SN54ACT573 . . . FK PACKAGE

3D
4D
5D
6D
7D

(TOP VIEW)

1

OE

2

1D

3

2D

4

3D

5

4D

6

5D

7

6D

8

7D

9

8D

GND

10

(TOP VIEW)

2D1DOE

3212019

4
5
6
7
8

910111213

8D

LE

20
19
18
17
16
15
14
13
12
11

V

CC

8Q

1Q

18
17
16
15
14

7Q

V
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE

CC

2Q
3Q
4Q
5Q
6Q

GND

T o ensure the high-impedance state during power up or power down, OE

should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

ORDERING INFORMA TION

T

A

PDIP – N Tube SN74ACT573N SN74ACT573N

–

–

–55°C to 125°C

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

SOP – NS Tape and reel SN74ACT573NSR ACT573
SSOP – DB Tape and reel SN74ACT573DBR AD573
TSSOP – PW Tape and reel SN74ACT573PWR AD573
CDIP – J Tube SNJ54ACT573J SNJ54ACT573J
CFP – W Tube SNJ54ACT573W SNJ54ACT573W
LCCC – FK Tube SNJ54ACT573FK SNJ54ACT573FK

PACKAGE

†

Tube SN74ACT573DW
Tape and reel SN74ACT573DWR

ORDERABLE

PART NUMBER

Copyright  2002, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.

TOP-SIDE
MARKING

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

SN54ACT573, SN74ACT573
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS

SCAS538D – OCTOBER 1995 – REVISED OCTOBER 2002

FUNCTION TABLE

INPUTS

OE LE D

L H H H
L HL L
L LX Q

H X X Z

logic diagram (positive logic)

1

OE

11

LE

(each latch)

OUTPUT

Q

0

1D

C1

2

To Seven Other Channels

1D

19

1Q

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Input voltage range, V
Output voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through, V
Package thermal impedance, θ

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

(VI < 0 or V

IK

(VO < 0 or V

OK

O

> VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

> VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

(VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

or GND ±200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 2): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 83°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

†

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UNIT

PARAMETER

TEST CONDITIONS

V

UNIT

I

50 µA

V

I

24 mA

V

I

50 µA

V

I

24 mA

V

∆I

‡

,

5.5 V

0.6

1.5

1.5

mA

UNIT

SN54ACT573, SN74ACT573

OCTAL D-TYPE TRANSPARENT LATCHES

WITH 3-STATE OUTPUTS

SCAS538D – OCTOBER 1995 – REVISED OCTOBER 2002

recommended operating conditions (see Note 3)

SN54ACT573 SN74ACT573

MIN MAX MIN MAX

V
V
V
V
V
I

OH

I

OL
∆t/∆v Input transition rise or fall rate 8 8 ns/V
T

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

†

Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms.

‡

This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.

Supply voltage 4.5 5.5 4.5 5.5 V

CC

High-level input voltage 2 2 V

IH

Low-level input voltage 0.8 0.8 V

IL

Input voltage 0 V

I

Output voltage 0 V

O

High-level output current –24 –24 mA
Low-level output current 24 24 mA

Operating free-air temperature –55 125 –40 85 °C

A

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

TA = 25°C SN54ACT573 SN74ACT573

MIN TYP MAX MIN MAX MIN MAX

I
I
I

C

OH

OL

OZ
I
CC

i

CC

CC

= –

OH

= –

OH

IOH = –50 mA
IOH = –75 mA

=

OL

=

OL

IOL = 50 mA
IOL = 75 mA
VO = VCC or GND 5.5 V ±0.25 ±5 ±2.5 µA
VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA
VI = VCC or GND, IO = 0 5.5 V 4 80 40 µA
One input at 3.4 V ,

Other inputs at GND or V
VI = VCC or GND 5 V 5 pF

†
†

†
†

CC

4.5 V 4.4 4.49 4.4 4.4

5.5 V 5.4 5.49 5.4 5.4

4.5 V 3.86 3.7 3.76

5.5 V 4.86 4.7 4.76

5.5 V 3.85

5.5 V 3.85

4.5 V 0.1 0.1 0.1

5.5 V 0.1 0.1 0.1

4.5 V 0.36 0.44 0.44

5.5 V 0.36 0.44 0.44

5.5 V 1.65

5.5 V 1.65

CC
CC

0 V
0 V

CC
CC

V
V

timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)

t

w
t

su
t

h

TA = 25°C SN54ACT573 SN74ACT573
MIN MAX MIN MAX MIN MAX

Pulse duration, LE high 3.5 5 4 ns
Setup time, data before LE↓ 3 4.5 3.5 ns
Hold time, data after LE↓ 0 1 0 ns

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

SN54ACT573, SN74ACT573

PARAMETER

UNIT

D

Q

ns

LE

Q

ns

OE

Q

ns

OE

Q

ns

OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS

SCAS538D – OCTOBER 1995 – REVISED OCTOBER 2002

switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)

FROM TO

(INPUT) (OUTPUT)

t

PLH

t

PHL

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

operating characteristics, VCC = 5 V, TA = 25°C

PARAMETER TEST CONDITIONS TYP UNIT

C

Power dissipation capacitance CL = 50 pF, f = 1 MHz 25 pF

pd

TA = 25°C SN54ACT573 SN74ACT573

MIN TYP MAX MIN MAX MIN MAX

2.5 6 10.5 1.5 13.5 2 12

2.5 6 10.5 1.5 13.5 2 12
3 6 10.5 1.5 13 2.5 12

2.5 5.5 9.5 1.5 12 2 10.5
2 5.5 10 1.5 11.5 1.5 11

1.5 5.5 9.5 1.5 11 1.5 10.5

2.5 6.5 11 1.5 13.5 1.5 12.5

1.5 5 8.5 1.5 10.5 1 9.5

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

From Output

Under Test

CL = 50 pF

(see Note A)

OCTAL D-TYPE TRANSPARENT LATCHES

SCAS538D – OCTOBER 1995 – REVISED OCTOBER 2002

PARAMETER MEASUREMENT INFORMATION

2 × V

CC

Open

500 Ω

500 Ω

S1

SN54ACT573, SN74ACT573

WITH 3-STATE OUTPUTS

TEST S1

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

Open

2 × V

Open

CC

LOAD CIRCUIT

t

w

Input

Input

Output

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one input transition per measurement.

1.5 V 1.5 V

VOLTAGE WAVEFORMS

1.5 V 1.5 V

t

PLH

50% V

VOLTAGE WAVEFORMS

CC

t

50% V

PHL

3 V

0 V

V

CC

V

3 V

0 V

OH

OL

Timing Input

Data Input

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2 × V

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

CC

1.5 V

t

su

1.5 V 1.5 V

VOLTAGE WAVEFORMS

1.5 V 1.5 V

t

PZL

50% V

t

PZH

50% V

VOLTAGE WAVEFORMS

CC

CC

t

h

VOL + 0.3 V

VOH – 0.3 V

t

PLZ

t

PHZ

3 V

0 V

3 V

0 V

3 V

0 V

≈V

V

OL

V

OH

≈0 V

CC

Figure 1. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5