SOIC
DW
ACT573
40°C to 85°C
SN54ACT573, SN74ACT573
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS538D – OCTOBER 1995 – REVISED OCTOBER 2002
D
4.5-V to 5.5-V VCC Operation
D
Inputs Accept Voltages to 5.5 V
D
Max tpd of 9.5 ns at 5 V
D
Inputs Are TTL-Voltage Compatible
description/ordering information
These 8-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. The devices
are particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight latches are D-type transparent latches.
When the latch-enable (LE) input is high, the Q
outputs follow the data (D) inputs. When LE is
taken low, the Q outputs are latched at the logic
levels set up at the D inputs.
A buffered output-enable (OE
to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
increased drive provide the capability to drive bus
lines in a bus-organized system without need for
interface or pullup components.
OE
does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
) input can be used
SN54ACT573 ...J OR W PACKAGE
SN74ACT573 . . . DB, DW, N, NS, OR PW P ACKAGE
SN54ACT573 . . . FK PACKAGE
3D
4D
5D
6D
7D
(TOP VIEW)
1
OE
2
1D
3
2D
4
3D
5
4D
6
5D
7
6D
8
7D
9
8D
GND
10
(TOP VIEW)
2D1DOE
3212019
4
5
6
7
8
910111213
8D
LE
20
19
18
17
16
15
14
13
12
11
V
CC
8Q
1Q
18
17
16
15
14
7Q
V
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
CC
2Q
3Q
4Q
5Q
6Q
GND
T o ensure the high-impedance state during power up or power down, OE
should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMA TION
T
A
PDIP – N Tube SN74ACT573N SN74ACT573N
–
–
–55°C to 125°C
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SOP – NS Tape and reel SN74ACT573NSR ACT573
SSOP – DB Tape and reel SN74ACT573DBR AD573
TSSOP – PW Tape and reel SN74ACT573PWR AD573
CDIP – J Tube SNJ54ACT573J SNJ54ACT573J
CFP – W Tube SNJ54ACT573W SNJ54ACT573W
LCCC – FK Tube SNJ54ACT573FK SNJ54ACT573FK
PACKAGE
†
Tube SN74ACT573DW
Tape and reel SN74ACT573DWR
ORDERABLE
PART NUMBER
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
TOP-SIDE
MARKING
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54ACT573, SN74ACT573
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS538D – OCTOBER 1995 – REVISED OCTOBER 2002
FUNCTION TABLE
INPUTS
OE LE D
L H H H
L HL L
L LX Q
H X X Z
logic diagram (positive logic)
1
OE
11
LE
(each latch)
OUTPUT
Q
0
1D
C1
2
To Seven Other Channels
1D
19
1Q
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Output voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through, V
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(VI < 0 or V
IK
(VO < 0 or V
OK
O
> VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
> VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
or GND ±200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 2): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 83°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
†
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
PARAMETER
TEST CONDITIONS
V
UNIT
I
50 µA
V
I
24 mA
V
I
50 µA
V
I
24 mA
V
∆I
‡
,
5.5 V
0.6
1.5
1.5
mA
UNIT
SN54ACT573, SN74ACT573
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS538D – OCTOBER 1995 – REVISED OCTOBER 2002
recommended operating conditions (see Note 3)
SN54ACT573 SN74ACT573
MIN MAX MIN MAX
V
V
V
V
V
I
OH
I
OL
∆t/∆v Input transition rise or fall rate 8 8 ns/V
T
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms.
‡
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
Supply voltage 4.5 5.5 4.5 5.5 V
CC
High-level input voltage 2 2 V
IH
Low-level input voltage 0.8 0.8 V
IL
Input voltage 0 V
I
Output voltage 0 V
O
High-level output current –24 –24 mA
Low-level output current 24 24 mA
Operating free-air temperature –55 125 –40 85 °C
A
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
TA = 25°C SN54ACT573 SN74ACT573
MIN TYP MAX MIN MAX MIN MAX
I
I
I
C
OH
OL
OZ
I
CC
i
CC
CC
= –
OH
= –
OH
IOH = –50 mA
IOH = –75 mA
=
OL
=
OL
IOL = 50 mA
IOL = 75 mA
VO = VCC or GND 5.5 V ±0.25 ±5 ±2.5 µA
VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA
VI = VCC or GND, IO = 0 5.5 V 4 80 40 µA
One input at 3.4 V ,
Other inputs at GND or V
VI = VCC or GND 5 V 5 pF
†
†
†
†
CC
4.5 V 4.4 4.49 4.4 4.4
5.5 V 5.4 5.49 5.4 5.4
4.5 V 3.86 3.7 3.76
5.5 V 4.86 4.7 4.76
5.5 V 3.85
5.5 V 3.85
4.5 V 0.1 0.1 0.1
5.5 V 0.1 0.1 0.1
4.5 V 0.36 0.44 0.44
5.5 V 0.36 0.44 0.44
5.5 V 1.65
5.5 V 1.65
CC
CC
0 V
0 V
CC
CC
V
V
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
t
w
t
su
t
h
TA = 25°C SN54ACT573 SN74ACT573
MIN MAX MIN MAX MIN MAX
Pulse duration, LE high 3.5 5 4 ns
Setup time, data before LE↓ 3 4.5 3.5 ns
Hold time, data after LE↓ 0 1 0 ns
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54ACT573, SN74ACT573
PARAMETER
UNIT
D
Q
ns
LE
Q
ns
OE
Q
ns
OE
Q
ns
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS538D – OCTOBER 1995 – REVISED OCTOBER 2002
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
FROM TO
(INPUT) (OUTPUT)
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
Power dissipation capacitance CL = 50 pF, f = 1 MHz 25 pF
pd
TA = 25°C SN54ACT573 SN74ACT573
MIN TYP MAX MIN MAX MIN MAX
2.5 6 10.5 1.5 13.5 2 12
2.5 6 10.5 1.5 13.5 2 12
3 6 10.5 1.5 13 2.5 12
2.5 5.5 9.5 1.5 12 2 10.5
2 5.5 10 1.5 11.5 1.5 11
1.5 5.5 9.5 1.5 11 1.5 10.5
2.5 6.5 11 1.5 13.5 1.5 12.5
1.5 5 8.5 1.5 10.5 1 9.5
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
CL = 50 pF
(see Note A)
OCTAL D-TYPE TRANSPARENT LATCHES
SCAS538D – OCTOBER 1995 – REVISED OCTOBER 2002
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
Open
500 Ω
500 Ω
S1
SN54ACT573, SN74ACT573
WITH 3-STATE OUTPUTS
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
Open
CC
LOAD CIRCUIT
t
w
Input
Input
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one input transition per measurement.
1.5 V 1.5 V
VOLTAGE WAVEFORMS
1.5 V 1.5 V
t
PLH
50% V
VOLTAGE WAVEFORMS
CC
t
50% V
PHL
3 V
0 V
V
CC
V
3 V
0 V
OH
OL
Timing Input
Data Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
CC
1.5 V
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
1.5 V 1.5 V
t
PZL
50% V
t
PZH
50% V
VOLTAGE WAVEFORMS
CC
CC
t
h
VOL + 0.3 V
VOH – 0.3 V
t
PLZ
t
PHZ
3 V
0 V
3 V
0 V
3 V
0 V
≈V
V
OL
V
OH
≈0 V
CC
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jun-2005
PACKAGING INFORMATION
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
5962-87664012A ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NC
5962-8766401RA ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NC
5962-8766401SA ACTIVE CFP W 20 TBD Call TI Level-NC-NC-NC
SN74ACT573DBLE OBSOLETE SSOP DB 20 TBD Call TI Call TI
SN74ACT573DBR ACTIVE SSOP DB 20 2000 Pb-Free
SN74ACT573DBRE4 ACTIVE SSOP DB 20 2000 Pb-Free
SN74ACT573DW ACTIVE SOIC DW 20 25 Pb-Free
SN74ACT573DWG4 ACTIVE SOIC DW 20 25 Green(RoHS &
no Sb/Br)
SN74ACT573DWR ACTIVE SOIC DW 20 2000 Pb-Free
SN74ACT573DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br)
SN74ACT573N ACTIVE PDIP N 20 20 Pb-Free
SN74ACT573NE4 ACTIVE PDIP N 20 20 Pb-Free
SN74ACT573NSR ACTIVE SO NS 20 2000 Pb-Free
SN74ACT573NSRE4 ACTIVE SO NS 20 2000 Pb-Free
SN74ACT573PW ACTIVE TSSOP PW 20 70 Pb-Free
SN74ACT573PWE4 ACTIVE TSSOP PW 20 70 Pb-Free
SN74ACT573PWLE OBSOLETE TSSOP PW 20 TBD Call TI Call TI
SN74ACT573PWR ACTIVE TSSOP PW 20 2000 Pb-Free
SN74ACT573PWRE4 ACTIVE TSSOP PW 20 2000 Pb-Free
SNJ54ACT573FK ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NC
SNJ54ACT573J ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(RoHS)
(RoHS)
(RoHS)
(RoHS)
(RoHS)
(RoHS)
(RoHS)
(RoHS)
(RoHS)
(RoHS)
(RoHS)
(RoHS)
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-NC-NC-NC
CU NIPDAU Level-NC-NC-NC
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
CU NIPDAU Level-1-250C-UNLIM
CU NIPDAU Level-1-250C-UNLIM
CU NIPDAU Level-1-250C-UNLIM
CU NIPDAU Level-1-250C-UNLIM
(3)
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
8-Jun-2005
Addendum-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A SQ
B SQ
19
20
22
23
24
25
21
12826 27
12
1314151618 17
0.020 (0,51)
0.010 (0,25)
MIN
0.342
(8,69)
0.442
0.640
0.739
0.938
1.141
A
0.358
(9,09)
0.458
(11,63)
0.660
(16,76)
0.761
(19,32)(18,78)
0.962
(24,43)
1.165
(29,59)
NO. OF
TERMINALS
**
11
10
9
8
7
6
5
432
20
28
44
52
68
84
0.020 (0,51)
0.010 (0,25)
(11,23)
(16,26)
(23,83)
(28,99)
MINMAX
0.307
(7,80)
0.406
(10,31)
0.495
(12,58)
0.495
(12,58)
0.850
(21,6)
1.047
(26,6)
0.080 (2,03)
0.064 (1,63)
B
MAX
0.358
(9,09)
0.458
(11,63)
0.560
(14,22)
0.560
(14,22)
0.858
(21,8)
1.063
(27,0)
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
4040140/D 10/96
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,65
28
1
2,00 MAX
0,38
0,22
15
14
A
0,05 MIN
0,15
5,60
5,00
M
8,20
7,40
Seating Plane
0,10
0,25
0,09
0°–ā8°
Gage Plane
0,25
0,95
0,55
PINS **
DIM
A MAX
A MIN
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
14
6,50
6,50
5,905,90
2016
7,50
6,90
24
8,50
28
10,50
9,907,90
30
10,50
9,90
38
12,90
12,30
4040065 /E 12/01
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65
1,20 MAX
14
0,30
0,19
8
4,50
4,30
PINS **
7
Seating Plane
0,15
0,05
8
1
A
DIM
6,60
6,20
14
0,10
M
0,10
0,15 NOM
0°–8°
2016
Gage Plane
24
0,25
0,75
0,50
28
A MAX
A MIN
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
4040064/F 01/97
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Mailing Address: Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2005, Texas Instruments Incorporated
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