Texas Instruments SN54ACT3632HFP Datasheet

SN54ACT3632

512 × 36 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SGBS310A – SEPTEMBER 1996 – REVISED APRIL 1998

D

Free-Running CLKA and CLKB Can Be
Asynchronous or Coincident

D

Two Independent 512 × 36 Clocked FIFOs
Buffering Data in Opposite Directions

D

Mailbox-Bypass Register for Each FIFO

D

Programmable Almost-Full and
Almost-Empty Flags

D

Microprocessor Interface Control Logic

D

IRA, ORA, AEA, and AFA Flags
Synchronized by CLKA

description

The SN54ACT3632 is a high-speed, low-power CMOS clocked bidirectional FIFO memory. It supports clock
frequencies up to 50 MHz and has read access times as fast as 11 ns. Two independent 512 × 36 dual-port
SRAM FIFOs on the chip buffer data in opposite directions. Each FIFO has flags to indicate empty and full
conditions and two programmable flags (almost full and almost empty) to indicate when a selected number of
words is stored in memory. Communication between each port can bypass the FIFOs via two 36-bit mailbox
registers. Each mailbox register has a flag to signal when new mail has been stored. Two or more devices can
be used in parallel to create wider data paths.

D

Released as DESC SMD (Standard
Microcircuit Drawing) 5962-9562801QYA

D

IRB, ORB, AEB, and AFB Flags
Synchronized by CLKB

D

Low-Power 0.8-µm Advanced CMOS
Technology

D

Supports Clock Frequencies up to 50 MHz

D

Fast Access Times of 13 ns

D

Packaged in 132-Pin Ceramic Quad Flat
Package

The SN54ACT3632 is a clocked FIFO, which means each port employs a synchronous interface. All data
transfers through a port are gated to the low-to-high transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asynchronous or coincident. The enables for each port
are arranged to provide a simple bidirectional interface between microprocessors and/or buses with
synchronous control.

The input-ready (IRA, IRB) flag and almost-full (AFA
port clock that writes data to its array. The output-ready (ORA, ORB) flag and almost-empty (AEA
of a FIFO are two-stage synchronized to the port clock that reads data from its array. Offset values for the
almost-full and almost-empty flags of both FIFOs can be programmed from port A.

The SN54ACT3632 is characterized for operation over the full military temperature range of –55°C to 125°C.
For more information on this device family, see the following application reports:

D

FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control

(literature number SCAA007)

D

Interfacing TI Clocked FIFOs With TI Floating-Point Digital Signal Processors

D

Metastability Performance of Clocked FIFOs

, AFB) flag of a FIFO are two-stage synchronized to the

, AEB) flag

(literature number SCAA005)

(literature number SCZA004)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1998, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.

1

SN54ACT3632
512 × 36 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SGBS310A – SEPTEMBER 1996 – REVISED APRIL 1998

CC

NC
B35
B34
B33
B32

GND

B31
B30
B29
B28
B27
B26

V

CC

B25
B24

GND

B23
B22
B21
B20
B19
B18

GND

B17
B16

V

CC

B15
B14
B13
B12

GND

NC

NC

NCNCV

17 1615 14 13 12 1110 9 8 7 6 5 4 3 2 1 132 130 128 126 124 122 120 118

18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 6667 68 70 72 74 76 78 80 8269 71 73 75 77 79 81 83

ENB

CLKB

CSB

W/RB

GND

IRB

ORB

AFB

HFP PACKAGE

CC

AEB

V

MBF1

(TOP VIEW)

MBB

FS1

RST2

GND

FS0

MBA

RST1

MBF2

131 129 127 125 123 121 119 117

AEA

CC

AFA

ORA

IRA

CSA

ENA

V

W/RA

GND

CLKA

NC

116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84

NC
NC
A35
A34
A33
A32
V

CC

A31
A30
GND
A29
A28
A27
A26
A25
A24
A23
GND
A22
V

CC

A21
A20
A19
A18
GND
A17
A16
A15
A14
A13
V

CC

A12
NC

NC – No internal connection

2

NC

B1 1

B9B8B7

B10

CC

B6

V

B5B4B3B2B1

GND

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B0

A0A1A2

GND

CC

A3A4A5

V

A6A7A8

GND

A9

A10

A1 1

NC

GND

NC

functional block diagram

CLKA

CSA

W/RA

ENA

MBA

RST1

Port-A

Control

Logic

FIFO1,

Mail1
Reset
Logic

SN54ACT3632

512 × 36 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SGBS310A – SEPTEMBER 1996 – REVISED APRIL 1998

MBF1

Mail1

Register

512 × 36

SRAM

Input Register

Write

Pointer

Output Register

Read

Pointer

36

IRA

AFA

FS0
FS1

A0–A35

ORA

AEA

36

FIFO1

9

FIFO2

Output Register

Status-Flag

Logic

Programmable-

Flag

Offset Registers

Status-Flag

Logic

Read

Pointer

512 × 36

SRAM

Mail2

Register

Write

Pointer

Input Register

36

FIFO2,

Mail2

Reset

Logic

Port-B

Control

Logic

ORB
AEB

B0–B35

IRB
AFB

RST2

CLKB
CSB
W/RB

ENB
MBB

MBF2

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3

SN54ACT3632
512 × 36 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SGBS310A – SEPTEMBER 1996 – REVISED APRIL 1998

Terminal Functions

TERMINAL

NAME

A0–A35 I/O Port-A data. The 36-bit bidirectional data port for side A.
AEA

AEB

AFA

AFB
B0–B35 I/O Port-B data. The 36-bit bidirectional data port for side B.

CLKA I

CLKB I

CSA

CSB
ENA I Port-A enable. ENA must be high to enable a low-to-high transition of CLKA to read or write data on port A.

ENB I Port-B enable. ENB must be high to enable a low-to-high transition of CLKB to read or write data on port B.

FS1, FS0 I

IRA

IRB

MBA I

MBB I

MBF1

MBF2

ORA

I/O DESCRIPTION

O

(port A)

(port B)

(port A)

(port B)

(port A)

(port B)

(port A)

Port-A almost-empty flag. Programmable flag synchronized to CLKA. AEA is low when the number of words in FIFO2
is less than or equal to the value in the almost-empty A offset register , X2.

O

Port-B almost-empty flag. Programmable flag synchronized to CLKB. AEB is low when the number of words in FIFO1
is less than or equal to the value in the almost-empty B offset register , X1.

O

Port-A almost-full flag. Programmable flag synchronized to CLKA. AFA is low when the number of empty locations
in FIFO1 is less than or equal to the value in the almost-full A offset register , Y1.

O

Port-B almost-full flag. Programmable flag synchronized to CLKB. AFB is low when the number of empty locations
in FIFO2 is less than or equal to the value in the almost-full B offset register , Y2.

Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A and can be
asynchronous or coincident to CLKB. IRA, ORA, AFA
CLKA.

Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B and can be
asynchronous or coincident to CLKA. IRB, ORB, AFB
CLKB.

Port-A chip select. CSA must be low to enable a low-to-high transition of CLKA to read or write data on port A. The

I

A0–A35 outputs are in the high-impedance state when CSA
Port-B chip select. CSB must be low to enable a low-to-high transition of CLKB to read or write data on port B. The

I

B0–B35 outputs are in the high-impedance state when CSB

Flag-offset selects. The low-to-high transition of a FIFO reset input latches the values of FS0 and FS1. If either FS0
or FS1 is high when a reset input goes high, one of three preset values is selected as the offset for the FIFO almost-full
and almost-empty flags. If both FIFOs are reset simultaneously and both FS0 and FS1 are low when RST1
go high, the first four writes to FIFO1 program the almost-full and almost-empty offsets for both FIFOs.

Input-ready flag. IRA is synchronized to the low-to-high transition of CLKA. When IRA is low, FIFO1 is full and writes

O

to its array are disabled. IRA is set low when FIFO1 is reset and is set high on the second low-to-high transition of
CLKA after reset.

Input-ready flag. IRB is synchronized to the low-to-high transition of CLKB. When IRB is low, FIFO2 is full and writes

O

to its array are disabled. IRB is set low when FIFO2 is reset and is set high on the second low-to-high transition of
CLKB after reset.

Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation. When
the A0–A35 outputs are active, a high level on MBA selects data from the mail2 register for output and a low level
selects FIFO2 output-register data for output.

Port-B mailbox select. A high level on MBB chooses a mailbox register for a port-B read or write operation. When
the B0–B35 outputs are active, a high level on MBB selects data from the mail1 register for output and a low level
selects FIFO1 output-register data for output.

Mail1 register flag. MBF1 is set low by the low-to-high transition of CLKA that writes data to the mail1 register. W rites
to the mail1 register are inhibited while MBF1

O

port-B read is selected and MBB is high. MBF1
Mail2 register flag. MBF2 is set low by the low-to-high transition of CLKB that writes data to the mail2 register. W rites

to the mail2 register are inhibited while MBF2

O

port-A read is selected and MBA is high. MBF2
Output-ready flag. ORA is synchronized to the low-to-high transition of CLKA. When ORA is low, FIFO2 is empty

O

and reads from its memory are disabled. Ready data is present on the output register of FIFO2 when ORA is high.
ORA is forced low when FIFO2 is reset and goes high on the third low-to-high transition of CLKA after a word is loaded
to empty memory.

, and AEA are all synchronized to the low-to-high transition of

, and AEB are synchronized to the low-to-high transition of

is low. MBF1 is set high by a low-to-high transition of CLKB when a

is set high when FIFO1 is reset.

is low. MBF2 is set high by a low-to-high transition of CLKA when a

also is set high when FIFO2 is reset.

is high.

is high.

and RST2

4

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SN54ACT3632

512 × 36 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SGBS310A – SEPTEMBER 1996 – REVISED APRIL 1998

Terminal Functions (Continued)

TERMINAL

NAME

ORB

RST1

RST2

W/RA

W/RB

I/O DESCRIPTION

Output-ready flag. ORB is synchronized to the low-to-high transition of CLKB. When ORB is low, FIFO1 is empty

O

(port B)

and reads from its memory are disabled. Ready data is present on the output register of FIFO1 when ORB is high.
ORB is forced low when FIFO1 is reset and goes high on the third low-to-high transition of CLKB after a word is loaded
to empty memory.

FIFO1 reset. To reset FIFO1, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must
occur while RST1

I

selection. FIFO1 must be reset upon power up before data is written to its RAM.
FIFO2 reset. To reset FIFO2, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must

occur while RST2

I

selection. FIFO2 must be reset upon power up before data is written to its RAM.
Port-A write/read select. A high on W/RA selects a write operation and a low selects a read operation on port A for

I

a low-to-high transition of CLKA. The A0–A35 outputs are in the high-impedance state when W/R
Port-B write/read select. A low on W/RB selects a write operation and a high selects a read operation on port B for

I

a low-to-high transition of CLKB. The B0–B35 outputs are in the high-impedance state when W

is low. The low-to-high transition of RST1 latches the status of FS0 and FS1 for AF A and AEB offset

is low. The low-to-high transition of RST2 latches the status of FS0 and FS1 for AFB and AEA offset

A is high.

/RB is low.

detailed description

reset

The FIFO memories of the SN54ACT3632 are reset separately by taking their reset (RST1
for at least four port-A clock (CLKA) and four port-B clock (CLKB) low-to-high transitions. The reset inputs can
switch asynchronously to the clocks. A FIFO reset initializes the internal read and write pointers and forces the
input-ready flag (IRA, IRB) low, the output-ready flag (ORA, ORB) low, the almost-empty flag (AEA
and the almost-full flag (AFA

, AFB) high. Resetting a FIFO also forces the mailbox flag (MBF1, MBF2) of the
parallel mailbox register high. After a FIFO is reset, its input-ready flag is set high after two clock cycles to begin
normal operation. A FIFO must be reset after power up before data is written to its memory.

, RST2) inputs low

, AEB) low,

A low-to-high transition on a FIFO reset (RST1

, RST2) input latches the value of the flag-select (FS0, FS1)

inputs for choosing the almost-full and almost-empty offset programming method.

almost-empty flag and almost-full flag offset programming

Four registers in the SN54ACT3632 are used to hold the offset values for the almost-empty and almost-full flags.
The port-B almost-empty flag (AEB
register is labeled X2. The port-A almost-full flag (AFA
flag (AFB

) offset register is labeled Y2. The index of each register name corresponds to its FIFO number . The

) offset register is labeled X1 and the port-A almost-empty flag (AEA) offset

) offset register is labeled Y1 and the port-B almost-full

offset registers can be loaded with preset values during the reset of a FIFO or they can be programmed from
port A (see Table 1).

Table 1. Flag Programming

FS1 FS0 RST1 RST2 X1 AND Y1 REGISTERS†X2 AND Y2 REGISTERS

H H ↑ X 64 X
H H X ↑ X 64
H L ↑ X 16 X
H L X ↑ X 16

L H ↑ X 8 X
L H X ↑ X 8
L L ↑ ↑ Programmed from port A Programmed from port A

†

X1 register holds the offset for AEB; Y1 register holds the offset for AFA.

‡

X2 register holds the offset for AEA

; Y2 register holds the offset for AFB.

‡

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5

SN54ACT3632
512 × 36 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SGBS310A – SEPTEMBER 1996 – REVISED APRIL 1998

almost-empty flag and almost-full flag offset programming (continued)

To load the almost-empty flag and almost-full flag offset registers of a FIFO with one of the three preset values
listed in Table 1, at least one of the flag-select inputs must be high during the low-to-high transition of its reset
input. For example, to load the preset value of 64 into X1 and Y1, FS0 and FS1 must be high when FIFO1 reset
(RST1

) returns high. Flag-offset registers associated with FIFO2 are loaded with one of the preset values in the
same way with FIFO2 reset (RST2
be reset simultaneously or at different times.

To program the X1, X2, Y1, and Y2 registers from port A, both FIFOs should be reset simultaneously with FS0
and FS1 low during the low-to-high transition of the reset inputs. After this reset is complete, the first four writes
to FIFO1 do not store data in RAM but load the offset registers in the order Y1, X1, Y2, X2. Each offset register
uses port-A (A8–A0) inputs, with A8 as the most-significant bit. Each register value can be programmed from
1 to 508. After all the offset registers are programmed from port A, the port-B input-ready flag (IRB) is set high
and both FIFOs begin normal operation.

FIFO write/read operation

). When using one of the preset values for the flag offsets, the FIFOs can

The state of the port-A data (A0–A35) outputs is controlled by the port-A chip select (CSA
write/read select (W/R
high. The A0–A35 outputs are active when both CSA

A). The A0–A35 outputs are in the high-impedance state when either CSA or W/RA is

and W/RA are low.

Data is loaded into FIFO1 from the A0–A35 inputs on a low-to-high transition of CLKA when CSA

) and the port-A

is low, W/RA
is high, ENA is high, MBA is low, and IRA is high. Data is read from FIFO2 to the A0–A35 outputs by a low-to-high
transition of CLKA when CSA

is low, W/RA is low , ENA is high, MBA is low , and ORA is high (see T able 2). FIFO

reads and writes on port A are independent of any concurrent port-B operation.

Table 2. Port-A Enable Function Table

CSA W/RA ENA MBA CLKA

H X X X X In high-impedance state None

L H L X X In high-impedance state None
L H H L ↑ In high-impedance state FIFO1 write
L H H H ↑ In high-impedance state Mail1 write
L L L L X Active, FIFO2 output register None
L L H L ↑ Active, FIFO2 output register FIFO2 read
L L L H X Active, mail2 register None
L L H H ↑ Active, mail2 register Mail2 read (set MBF2 high)

A0–A35 OUTPUTS PORT FUNCTION

The port-B control signals are identical to those of port A with the exception that the port-B write/read select
(W

/RB) is the inverse of the port-A write/read select (W/RA). The state of the port-B data (B0–B35) outputs is
controlled by the port-B chip select (CSB
the high-impedance state when either CSB

) and the port-B write/read select (W/RB). The B0–B35 outputs are in

is high or W/RB is low. The B0–B35 outputs are active when CSB

is low and W/RB is high.
Data is loaded into FIFO2 from the B0–B35 inputs on a low-to-high transition of CLKB when CSB

is low, W/RB
is low, ENB is high, MBB is low , and IRB is high. Data is read from FIFO1 to the B0–B35 outputs by a low-to-high
transition of CLKB when CSB

is low, W/RB is high, ENB is high, MBB is low , and ORB is high (see T able 3). FIFO

reads and writes on port B are independent of any concurrent port-A operation.

6

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IN FIFO1

†‡

FIFO write/read operation (continued)

Table 3. Port-B Enable Function Table

SN54ACT3632

512 × 36 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SGBS310A – SEPTEMBER 1996 – REVISED APRIL 1998

CSB W/RB ENB MBB CLKB

H X X X X In high-impedance state None

L L L X X In high-impedance state None
L L H L ↑ In high-impedance state FIFO2 write
L L H H ↑ In high-impedance state Mail2 write
L H L L X Active, FIFO1 output register None
L H H L ↑ Active, FIFO1 output register FIFO1 read
L H L H X Active, mail1 register None
L H H H ↑ Active, mail1 register Mail1 read (set MBF1 high)

B0–B35 OUTPUTS PORT FUNCTION

The setup- and hold-time constraints to the port clocks for the port-chip selects and write/read selects are only
for enabling write and read operations and are not related to high-impedance control of the data outputs. If a
port enable is low during a clock cycle, the port-chip select and write/read select may change states during the
setup- and hold-time window of the cycle.

When a FIFO output-ready flag is low, the next data word is sent to the FIFO output register automatically by
the low-to-high transition of the port clock that sets the output-ready flag high. When the output-ready flag is
high, an available data word is clocked to the FIFO output register only when a FIFO read is selected by the
port’s chip select, write/read select, enable, and mailbox select.

synchronized FIFO flags

Each FIFO is synchronized to its port clock through at least two flip-flop stages. This is done to improve
flag-signal reliability by reducing the probability of metastable events when CLKA and CLKB operate
asynchronously to one another. ORA, AEA

, IRA, and AFA are synchronized to CLKA. ORB, AEB, IRB, and AFB

are synchronized to CLKB. Tables 4 and 5 show the relationship of each port flag to FIFO1 and FIFO2.

Table 4. FIFO1 Flag Operation

NUMBER OF WORDS

0 L L H H

1 to X1 H L H H

(X1 + 1) to [512 – (Y1 + 1)] H H H H

(512 – Y1) to 511 H H L H

512 H H L L

†

X1 is the almost-empty offset for FIFO1 used by AEB. Y1 is the almost-full
offset for FIFO1 used by AFA
of FIFO1 or programmed from port A.

‡

When a word loaded to an empty FIFO is shifted to the output register , its
previous FIFO memory location is free.

SYNCHRONIZED

TO CLKB

ORB AEB AFA IRA

. Both X1 and Y1 are selected during a reset

SYNCHRONIZED

TO CLKA

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7

SN54ACT3632

IN FIFO2

†‡

512 × 36 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SGBS310A – SEPTEMBER 1996 – REVISED APRIL 1998

Table 5. FIFO2 Flag Operation

NUMBER OF WORDS

0 L L H H

1 to X2 H L H H

(X2 + 1) to [512 – (Y2 + 1)] H H H H

(512 – Y2) to 511 H H L H

512 H H L L

†

X2 is the almost-empty offset for FIFO2 used by AEA
offset for FIFO2 used by AFB
of FIFO2 or programmed from port A.

‡

When a word loaded to an empty FIFO is shifted to the output register , its
previous FIFO memory location is free.

SYNCHRONIZED

TO CLKA

ORA AEA AFB IRB

. Both X2 and Y2 are selected during a reset

SYNCHRONIZED

TO CLKB

. Y2 is the almost-full

output-ready flags (ORA, ORB)

The output-ready flag of a FIFO is synchronized to the port clock that reads data from its array. When the
output-ready flag is high, new data is present in the FIFO output register. When the output-ready flag is low , the
previous data word is present in the FIFO output register and attempted FIFO reads are ignored.

A FIFO read pointer is incremented each time a new word is clocked to its output register. The state machine
that controls an output-ready flag monitors a write-pointer and read-pointer comparator that indicates when the
FIFO SRAM status is empty , empty+1, or empty+2. From the time a word is written to a FIFO, it can be shifted
to the FIFO output register in a minimum of three cycles of the output-ready flag synchronizing clock; therefore,
an output-ready flag is low if a word in memory is the next data to be sent to the FIFO output register and three
cycles of the port clock that reads data from the FIFO have not elapsed since the time the word was written.
The output-ready flag of the FIFO remains low until the third low-to-high transition of the synchronizing clock
occurs, simultaneously forcing the output-ready flag high and shifting the word to the FIFO output register.

A low-to-high transition on an output-ready flag synchronizing clock begins the first synchronization cycle of a
write if the clock transition occurs at time t

, or greater, after the write. Otherwise, the subsequent clock cycle

sk1

can be the first synchronization cycle (see Figures 7 and 8).

input-ready flags (IRA, IRB)

The input-ready flag of a FIFO is synchronized to the port clock that writes data to its array . When the input-ready
flag is high, a memory location is free in the SRAM to receive new data. No memory locations are free when
the input-ready flag is low and attempted writes to the FIFO are ignored.

Each time a word is written to a FIFO, its write pointer is incremented. The state machine that controls an
input-ready flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM
status is full, full–1, or full–2. From the time a word is read from a FIFO, its previous memory location is ready
to be written in a minimum of two cycles of the input-ready flag synchronizing clock; therefore, an input-ready
flag is low if less than two cycles of the input-ready flag synchronizing clock have elapsed since the next memory
write location has been read. The second low-to-high transition on the input-ready flag synchronizing clock after
the read sets the input-ready flag high.

A low-to-high transition on an input-ready flag synchronizing clock begins the first synchronization cycle of a
read if the clock transition occurs at time t

, or greater, after the read. Otherwise, the subsequent clock cycle

sk1

can be the first synchronization cycle (see Figures 9 and 10).

8

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