Datasheet SN54ACT3632HFP Datasheet (Texas Instruments)

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SN54ACT3632

512 × 36 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SGBS310A – SEPTEMBER 1996 – REVISED APRIL 1998

Free-Running CLKA and CLKB Can Be Asynchronous or Coincident

Two Independent 512 × 36 Clocked FIFOs Buffering Data in Opposite Directions

Mailbox-Bypass Register for Each FIFO

Programmable Almost-Full and Almost-Empty Flags

Microprocessor Interface Control Logic

IRA, ORA, AEA, and AFA Flags Synchronized by CLKA

description

The SN54ACT3632 is a high-speed, low-power CMOS clocked bidirectional FIFO memory. It supports clock frequencies up to 50 MHz and has read access times as fast as 11 ns. Two independent 512 × 36 dual-port SRAM FIFOs on the chip buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions and two programmable flags (almost full and almost empty) to indicate when a selected number of words is stored in memory. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Two or more devices can be used in parallel to create wider data paths.

Released as DESC SMD (Standard Microcircuit Drawing) 5962-9562801QYA

IRB, ORB, AEB, and AFB Flags Synchronized by CLKB

Low-Power 0.8-µm Advanced CMOS Technology

Supports Clock Frequencies up to 50 MHz

Fast Access Times of 13 ns

Packaged in 132-Pin Ceramic Quad Flat Package

The SN54ACT3632 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.

The input-ready (IRA, IRB) flag and almost-full (AFA port clock that writes data to its array. The output-ready (ORA, ORB) flag and almost-empty (AEA of a FIFO are two-stage synchronized to the port clock that reads data from its array. Offset values for the almost-full and almost-empty flags of both FIFOs can be programmed from port A.

The SN54ACT3632 is characterized for operation over the full military temperature range of –55°C to 125°C. For more information on this device family, see the following application reports:

FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control

(literature number SCAA007)

Interfacing TI Clocked FIFOs With TI Floating-Point Digital Signal Processors

Metastability Performance of Clocked FIFOs

, AFB) flag of a FIFO are two-stage synchronized to the

, AEB) flag

(literature number SCAA005)

(literature number SCZA004)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

SN54ACT3632 512 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SGBS310A – SEPTEMBER 1996 – REVISED APRIL 1998

NC B35 B34 B33 B32

GND

B31 B30 B29 B28 B27 B26

B25 B24

GND

B23 B22 B21 B20 B19 B18

GND

B17 B16

B15 B14 B13 B12

GND

NCNCV

17 1615 14 13 12 1110 9 8 7 6 5 4 3 2 1 132 130 128 126 124 122 120 118

18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 6667 68 70 72 74 76 78 80 8269 71 73 75 77 79 81 83

ENB

CLKB

CSB

W/RB

GND

IRB

ORB

AFB

HFP PACKAGE

AEB

MBF1

(TOP VIEW)

MBB

FS1

RST2

GND

FS0

MBA

RST1

MBF2

131 129 127 125 123 121 119 117

AEA

AFA

ORA

IRA

CSA

ENA

W/RA

GND

CLKA

116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84

NC NC A35 A34 A33 A32 V

A31 A30 GND A29 A28 A27 A26 A25 A24 A23 GND A22 V

A21 A20 A19 A18 GND A17 A16 A15 A14 A13 V

A12 NC

NC – No internal connection

B1 1

B9B8B7

B10

B5B4B3B2B1

GND

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A0A1A2

GND

A3A4A5

A6A7A8

GND

A10

A1 1

GND

functional block diagram

CLKA

CSA

W/RA

ENA

MBA

RST1

Port-A

Control

Logic

FIFO1,

Mail1 Reset Logic

SN54ACT3632

512 × 36 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SGBS310A – SEPTEMBER 1996 – REVISED APRIL 1998

MBF1

Mail1

512 × 36

SRAM

Input Register

Write

Pointer

Output Register

Read

Pointer

IRA

AFA

FS0 FS1

A0–A35

ORA

AEA

FIFO1

FIFO2

Output Register

Status-Flag

Logic

Programmable-

Flag

Offset Registers

Status-Flag

Logic

Read

Pointer

512 × 36

SRAM

Mail2

Write

Pointer

Input Register

FIFO2,

Mail2

Reset

Logic

Port-B

Control

Logic

ORB AEB

B0–B35

IRB AFB

RST2

CLKB CSB W/RB

ENB MBB

MBF2

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SN54ACT3632 512 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SGBS310A – SEPTEMBER 1996 – REVISED APRIL 1998

Terminal Functions

TERMINAL

NAME

A0–A35 I/O Port-A data. The 36-bit bidirectional data port for side A. AEA

AEB

AFA

AFB B0–B35 I/O Port-B data. The 36-bit bidirectional data port for side B.

CLKA I

CLKB I

CSA

CSB ENA I Port-A enable. ENA must be high to enable a low-to-high transition of CLKA to read or write data on port A.

ENB I Port-B enable. ENB must be high to enable a low-to-high transition of CLKB to read or write data on port B.

FS1, FS0 I

IRA

IRB

MBA I

MBB I

MBF1

MBF2

ORA

I/O DESCRIPTION

(port A)

(port B)

(port A)

(port B)

(port A)

(port B)

(port A)

Port-A almost-empty flag. Programmable flag synchronized to CLKA. AEA is low when the number of words in FIFO2 is less than or equal to the value in the almost-empty A offset register , X2.

Port-B almost-empty flag. Programmable flag synchronized to CLKB. AEB is low when the number of words in FIFO1 is less than or equal to the value in the almost-empty B offset register , X1.

Port-A almost-full flag. Programmable flag synchronized to CLKA. AFA is low when the number of empty locations in FIFO1 is less than or equal to the value in the almost-full A offset register , Y1.

Port-B almost-full flag. Programmable flag synchronized to CLKB. AFB is low when the number of empty locations in FIFO2 is less than or equal to the value in the almost-full B offset register , Y2.

Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous or coincident to CLKB. IRA, ORA, AFA CLKA.

Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous or coincident to CLKA. IRB, ORB, AFB CLKB.

Port-A chip select. CSA must be low to enable a low-to-high transition of CLKA to read or write data on port A. The

A0–A35 outputs are in the high-impedance state when CSA Port-B chip select. CSB must be low to enable a low-to-high transition of CLKB to read or write data on port B. The

B0–B35 outputs are in the high-impedance state when CSB

Flag-offset selects. The low-to-high transition of a FIFO reset input latches the values of FS0 and FS1. If either FS0 or FS1 is high when a reset input goes high, one of three preset values is selected as the offset for the FIFO almost-full and almost-empty flags. If both FIFOs are reset simultaneously and both FS0 and FS1 are low when RST1 go high, the first four writes to FIFO1 program the almost-full and almost-empty offsets for both FIFOs.

Input-ready flag. IRA is synchronized to the low-to-high transition of CLKA. When IRA is low, FIFO1 is full and writes

to its array are disabled. IRA is set low when FIFO1 is reset and is set high on the second low-to-high transition of CLKA after reset.

Input-ready flag. IRB is synchronized to the low-to-high transition of CLKB. When IRB is low, FIFO2 is full and writes

to its array are disabled. IRB is set low when FIFO2 is reset and is set high on the second low-to-high transition of CLKB after reset.

Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation. When the A0–A35 outputs are active, a high level on MBA selects data from the mail2 register for output and a low level selects FIFO2 output-register data for output.

Port-B mailbox select. A high level on MBB chooses a mailbox register for a port-B read or write operation. When the B0–B35 outputs are active, a high level on MBB selects data from the mail1 register for output and a low level selects FIFO1 output-register data for output.

Mail1 register flag. MBF1 is set low by the low-to-high transition of CLKA that writes data to the mail1 register. W rites to the mail1 register are inhibited while MBF1

port-B read is selected and MBB is high. MBF1 Mail2 register flag. MBF2 is set low by the low-to-high transition of CLKB that writes data to the mail2 register. W rites

to the mail2 register are inhibited while MBF2

port-A read is selected and MBA is high. MBF2 Output-ready flag. ORA is synchronized to the low-to-high transition of CLKA. When ORA is low, FIFO2 is empty

and reads from its memory are disabled. Ready data is present on the output register of FIFO2 when ORA is high. ORA is forced low when FIFO2 is reset and goes high on the third low-to-high transition of CLKA after a word is loaded to empty memory.

, and AEA are all synchronized to the low-to-high transition of

, and AEB are synchronized to the low-to-high transition of

is low. MBF1 is set high by a low-to-high transition of CLKB when a

is set high when FIFO1 is reset.

is low. MBF2 is set high by a low-to-high transition of CLKA when a

also is set high when FIFO2 is reset.

is high.

and RST2

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SN54ACT3632

512 × 36 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SGBS310A – SEPTEMBER 1996 – REVISED APRIL 1998

Terminal Functions (Continued)

TERMINAL

NAME

ORB

RST1

RST2

W/RA

W/RB

I/O DESCRIPTION

Output-ready flag. ORB is synchronized to the low-to-high transition of CLKB. When ORB is low, FIFO1 is empty

(port B)

and reads from its memory are disabled. Ready data is present on the output register of FIFO1 when ORB is high. ORB is forced low when FIFO1 is reset and goes high on the third low-to-high transition of CLKB after a word is loaded to empty memory.

FIFO1 reset. To reset FIFO1, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur while RST1

selection. FIFO1 must be reset upon power up before data is written to its RAM. FIFO2 reset. To reset FIFO2, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must

occur while RST2

selection. FIFO2 must be reset upon power up before data is written to its RAM. Port-A write/read select. A high on W/RA selects a write operation and a low selects a read operation on port A for

a low-to-high transition of CLKA. The A0–A35 outputs are in the high-impedance state when W/R Port-B write/read select. A low on W/RB selects a write operation and a high selects a read operation on port B for

a low-to-high transition of CLKB. The B0–B35 outputs are in the high-impedance state when W

is low. The low-to-high transition of RST1 latches the status of FS0 and FS1 for AF A and AEB offset

is low. The low-to-high transition of RST2 latches the status of FS0 and FS1 for AFB and AEA offset

A is high.

/RB is low.

detailed description

reset

The FIFO memories of the SN54ACT3632 are reset separately by taking their reset (RST1 for at least four port-A clock (CLKA) and four port-B clock (CLKB) low-to-high transitions. The reset inputs can switch asynchronously to the clocks. A FIFO reset initializes the internal read and write pointers and forces the input-ready flag (IRA, IRB) low, the output-ready flag (ORA, ORB) low, the almost-empty flag (AEA and the almost-full flag (AFA

, AFB) high. Resetting a FIFO also forces the mailbox flag (MBF1, MBF2) of the parallel mailbox register high. After a FIFO is reset, its input-ready flag is set high after two clock cycles to begin normal operation. A FIFO must be reset after power up before data is written to its memory.

, RST2) inputs low

, AEB) low,

A low-to-high transition on a FIFO reset (RST1

, RST2) input latches the value of the flag-select (FS0, FS1)

inputs for choosing the almost-full and almost-empty offset programming method.

almost-empty flag and almost-full flag offset programming

Four registers in the SN54ACT3632 are used to hold the offset values for the almost-empty and almost-full flags. The port-B almost-empty flag (AEB register is labeled X2. The port-A almost-full flag (AFA flag (AFB

) offset register is labeled Y2. The index of each register name corresponds to its FIFO number . The

) offset register is labeled X1 and the port-A almost-empty flag (AEA) offset

) offset register is labeled Y1 and the port-B almost-full

offset registers can be loaded with preset values during the reset of a FIFO or they can be programmed from port A (see Table 1).

Table 1. Flag Programming

FS1 FS0 RST1 RST2 X1 AND Y1 REGISTERS†X2 AND Y2 REGISTERS

H H ↑ X 64 X H H X ↑ X 64 H L ↑ X 16 X H L X ↑ X 16

L H ↑ X 8 X L H X ↑ X 8 L L ↑ ↑ Programmed from port A Programmed from port A

†

X1 register holds the offset for AEB; Y1 register holds the offset for AFA.

‡

X2 register holds the offset for AEA

; Y2 register holds the offset for AFB.

‡

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SN54ACT3632 512 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SGBS310A – SEPTEMBER 1996 – REVISED APRIL 1998

almost-empty flag and almost-full flag offset programming (continued)

To load the almost-empty flag and almost-full flag offset registers of a FIFO with one of the three preset values listed in Table 1, at least one of the flag-select inputs must be high during the low-to-high transition of its reset input. For example, to load the preset value of 64 into X1 and Y1, FS0 and FS1 must be high when FIFO1 reset (RST1

) returns high. Flag-offset registers associated with FIFO2 are loaded with one of the preset values in the same way with FIFO2 reset (RST2 be reset simultaneously or at different times.

To program the X1, X2, Y1, and Y2 registers from port A, both FIFOs should be reset simultaneously with FS0 and FS1 low during the low-to-high transition of the reset inputs. After this reset is complete, the first four writes to FIFO1 do not store data in RAM but load the offset registers in the order Y1, X1, Y2, X2. Each offset register uses port-A (A8–A0) inputs, with A8 as the most-significant bit. Each register value can be programmed from 1 to 508. After all the offset registers are programmed from port A, the port-B input-ready flag (IRB) is set high and both FIFOs begin normal operation.

FIFO write/read operation

). When using one of the preset values for the flag offsets, the FIFOs can

The state of the port-A data (A0–A35) outputs is controlled by the port-A chip select (CSA write/read select (W/R high. The A0–A35 outputs are active when both CSA

A). The A0–A35 outputs are in the high-impedance state when either CSA or W/RA is

and W/RA are low.

Data is loaded into FIFO1 from the A0–A35 inputs on a low-to-high transition of CLKA when CSA

) and the port-A

is low, W/RA is high, ENA is high, MBA is low, and IRA is high. Data is read from FIFO2 to the A0–A35 outputs by a low-to-high transition of CLKA when CSA

is low, W/RA is low , ENA is high, MBA is low , and ORA is high (see T able 2). FIFO

reads and writes on port A are independent of any concurrent port-B operation.

Table 2. Port-A Enable Function Table

CSA W/RA ENA MBA CLKA

H X X X X In high-impedance state None

L H L X X In high-impedance state None L H H L ↑ In high-impedance state FIFO1 write L H H H ↑ In high-impedance state Mail1 write L L L L X Active, FIFO2 output register None L L H L ↑ Active, FIFO2 output register FIFO2 read L L L H X Active, mail2 register None L L H H ↑ Active, mail2 register Mail2 read (set MBF2 high)

A0–A35 OUTPUTS PORT FUNCTION

The port-B control signals are identical to those of port A with the exception that the port-B write/read select (W

/RB) is the inverse of the port-A write/read select (W/RA). The state of the port-B data (B0–B35) outputs is controlled by the port-B chip select (CSB the high-impedance state when either CSB

) and the port-B write/read select (W/RB). The B0–B35 outputs are in

is high or W/RB is low. The B0–B35 outputs are active when CSB

is low and W/RB is high. Data is loaded into FIFO2 from the B0–B35 inputs on a low-to-high transition of CLKB when CSB

is low, W/RB is low, ENB is high, MBB is low , and IRB is high. Data is read from FIFO1 to the B0–B35 outputs by a low-to-high transition of CLKB when CSB

is low, W/RB is high, ENB is high, MBB is low , and ORB is high (see T able 3). FIFO

reads and writes on port B are independent of any concurrent port-A operation.

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IN FIFO1

†‡

FIFO write/read operation (continued)

Table 3. Port-B Enable Function Table

SN54ACT3632

512 × 36 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SGBS310A – SEPTEMBER 1996 – REVISED APRIL 1998

CSB W/RB ENB MBB CLKB

H X X X X In high-impedance state None

L L L X X In high-impedance state None L L H L ↑ In high-impedance state FIFO2 write L L H H ↑ In high-impedance state Mail2 write L H L L X Active, FIFO1 output register None L H H L ↑ Active, FIFO1 output register FIFO1 read L H L H X Active, mail1 register None L H H H ↑ Active, mail1 register Mail1 read (set MBF1 high)

B0–B35 OUTPUTS PORT FUNCTION

The setup- and hold-time constraints to the port clocks for the port-chip selects and write/read selects are only for enabling write and read operations and are not related to high-impedance control of the data outputs. If a port enable is low during a clock cycle, the port-chip select and write/read select may change states during the setup- and hold-time window of the cycle.

When a FIFO output-ready flag is low, the next data word is sent to the FIFO output register automatically by the low-to-high transition of the port clock that sets the output-ready flag high. When the output-ready flag is high, an available data word is clocked to the FIFO output register only when a FIFO read is selected by the port’s chip select, write/read select, enable, and mailbox select.

synchronized FIFO flags

Each FIFO is synchronized to its port clock through at least two flip-flop stages. This is done to improve flag-signal reliability by reducing the probability of metastable events when CLKA and CLKB operate asynchronously to one another. ORA, AEA

, IRA, and AFA are synchronized to CLKA. ORB, AEB, IRB, and AFB

are synchronized to CLKB. Tables 4 and 5 show the relationship of each port flag to FIFO1 and FIFO2.

Table 4. FIFO1 Flag Operation

NUMBER OF WORDS

0 L L H H

1 to X1 H L H H

(X1 + 1) to [512 – (Y1 + 1)] H H H H

(512 – Y1) to 511 H H L H

512 H H L L

†

X1 is the almost-empty offset for FIFO1 used by AEB. Y1 is the almost-full offset for FIFO1 used by AFA of FIFO1 or programmed from port A.

‡

When a word loaded to an empty FIFO is shifted to the output register , its previous FIFO memory location is free.

SYNCHRONIZED

TO CLKB

ORB AEB AFA IRA

. Both X1 and Y1 are selected during a reset

SYNCHRONIZED

TO CLKA

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SN54ACT3632

IN FIFO2

†‡

512 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SGBS310A – SEPTEMBER 1996 – REVISED APRIL 1998

Table 5. FIFO2 Flag Operation

NUMBER OF WORDS

0 L L H H

1 to X2 H L H H

(X2 + 1) to [512 – (Y2 + 1)] H H H H

(512 – Y2) to 511 H H L H

512 H H L L

†

X2 is the almost-empty offset for FIFO2 used by AEA offset for FIFO2 used by AFB of FIFO2 or programmed from port A.

‡

When a word loaded to an empty FIFO is shifted to the output register , its previous FIFO memory location is free.

SYNCHRONIZED

TO CLKA

ORA AEA AFB IRB

. Both X2 and Y2 are selected during a reset

SYNCHRONIZED

TO CLKB

. Y2 is the almost-full

output-ready flags (ORA, ORB)

The output-ready flag of a FIFO is synchronized to the port clock that reads data from its array. When the output-ready flag is high, new data is present in the FIFO output register. When the output-ready flag is low , the previous data word is present in the FIFO output register and attempted FIFO reads are ignored.

A FIFO read pointer is incremented each time a new word is clocked to its output register. The state machine that controls an output-ready flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM status is empty , empty+1, or empty+2. From the time a word is written to a FIFO, it can be shifted to the FIFO output register in a minimum of three cycles of the output-ready flag synchronizing clock; therefore, an output-ready flag is low if a word in memory is the next data to be sent to the FIFO output register and three cycles of the port clock that reads data from the FIFO have not elapsed since the time the word was written. The output-ready flag of the FIFO remains low until the third low-to-high transition of the synchronizing clock occurs, simultaneously forcing the output-ready flag high and shifting the word to the FIFO output register.

A low-to-high transition on an output-ready flag synchronizing clock begins the first synchronization cycle of a write if the clock transition occurs at time t

, or greater, after the write. Otherwise, the subsequent clock cycle

sk1

can be the first synchronization cycle (see Figures 7 and 8).

input-ready flags (IRA, IRB)

The input-ready flag of a FIFO is synchronized to the port clock that writes data to its array . When the input-ready flag is high, a memory location is free in the SRAM to receive new data. No memory locations are free when the input-ready flag is low and attempted writes to the FIFO are ignored.

Each time a word is written to a FIFO, its write pointer is incremented. The state machine that controls an input-ready flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM status is full, full–1, or full–2. From the time a word is read from a FIFO, its previous memory location is ready to be written in a minimum of two cycles of the input-ready flag synchronizing clock; therefore, an input-ready flag is low if less than two cycles of the input-ready flag synchronizing clock have elapsed since the next memory write location has been read. The second low-to-high transition on the input-ready flag synchronizing clock after the read sets the input-ready flag high.

A low-to-high transition on an input-ready flag synchronizing clock begins the first synchronization cycle of a read if the clock transition occurs at time t

, or greater, after the read. Otherwise, the subsequent clock cycle

sk1

can be the first synchronization cycle (see Figures 9 and 10).

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SN54ACT3632

512 × 36 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SGBS310A – SEPTEMBER 1996 – REVISED APRIL 1998

almost-empty flags (AEA, AEB)

The almost-empty flag of a FIFO is synchronized to the port clock that reads data from its array. The state machine that controls an almost-empty flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM status is almost empty , almost empty+1, or almost empty+2. The almost-empty state is defined by the contents of register X1 for AEB values during a FIFO reset or programmed from port A (see

programming

contains (X + 1) or more words. A data word present in the FIFO output register has been read from memory . Two low-to-high transitions of the almost-empty flag synchronizing clock are required after a FIFO write for its

almost-empty flag to reflect the new level of fill. Therefore, the almost-empty flag of a FIFO containing (X + 1) or more words remains low if two cycles of its synchronizing clock have not elapsed since the write that filled the memory to the (X + 1) level. An almost-empty flag is set high by the second low-to-high transition of its synchronizing clock after the FIFO write that fills memory to the (X + 1) level. A low-to-high transition of an almost-empty flag synchronizing clock begins the first synchronization cycle if it occurs at time t after the write that fills the FIFO to (X + 1) words. Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see Figures 11 and 12).

). An almost-empty flag is low when its FIFO contains X or fewer words and is high when its FIFO

almost-full flags (AFA, AFB)

The almost-full flag of a FIFO is synchronized to the port clock that writes data to its array . The state machine that controls an almost-full flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM status is almost full, almost full–1, or almost full–2. The almost-full state is defined by the contents of register Y1 for AFA or programmed from port A (see is low when its FIFO contains (512 – Y) or more words and is high when its FIFO contains [512 – (Y + 1)] or less words. A data word present in the FIFO output register has been read from memory.

and register Y2 for AFB. These registers are loaded with preset values during a FIFO reset

almost-empty flag and almost-full flag offset programming

and register X2 for AEA. These registers are loaded with preset

almost-empty flag and almost-full flag offset

sk2

). An almost-full flag

, or greater,

Two low-to-high transitions of the almost-full flag synchronizing clock are required after a FIFO read for its almost-full flag to reflect the new level of fill. Therefore, the almost-full flag of a FIFO containing [512 – (Y + 1)] or fewer words remains low if two cycles of its synchronizing clock have not elapsed since the read that reduced the number of words in memory to [512 – (Y + 1)]. An almost-full flag is set high by the second low-to-high transition of its synchronizing clock after the FIFO read that reduces the number of words in memory to [512 – (Y + 1)]. A low-to-high transition of an almost-full flag synchronizing clock begins the first synchronization cycle if it occurs at time t [512 – (Y + 1)]. Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see Figures 13 and 14).

mailbox registers

Each FIFO has a 36-bit bypass register to pass command and control information between port A and port B without putting it in queue. The mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO for a port-data-transfer operation. A low-to-high transition on CLKA writes A0–A35 data to the mail1 register when a port-A write is selected by CSA writes B0–B35 data to the mail2 register when a port-B write is selected by CSB high. Writing data to a mail register sets its corresponding flag (MBF1 register are ignored while the mail flag is low.

When data outputs of a port are active, the data on the bus comes from the FIFO output register when the port mailbox select input is low and from the mail register when the port-mailbox select input is high. The mail1 register flag (MBF1 W

/RB, and ENB and with MBB high. The mail2 register flag (MBF2) is set high by a low-to-high transition on CLKA when a port-A read is selected by CSA remains intact after it is read and changes only when new data is written to the register.

) is set high by a low-to-high transition on CLKB when a port-B read is selected by CSB,

, or greater, after the read that reduces the number of words in memory to

sk2

, W/RA, and ENA and with MBA high. A low-to-high transition on CLKB

, W/RB, and ENB and with MBB

or MBF2) low. Attempted writes to a mail

, W/RA, and ENA and with MBA high. The data in a mail register

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ACT3632

ППППППППППП

ÏÏÏ

512 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SGBS310A – SEPTEMBER 1996 – REVISED APRIL 1998

CLKA

CLKB

su(RS)

RST1

su(FS)

h(RS)

h(FS)

FS1, FS0

pd(C-IR)

IRA

pd(C-OR)

ORB

pd(R-F)

AEB

pd(R-F)

AFA

pd(R-F)

MBF1

Figure 1. FIFO1 Reset Loading X1 and Y1 With a Preset Value of Eight

†

FIFO2 is reset in the same manner to load X2 and Y2 with a preset value.

CLKA

RST1,

RST2

FS1, FS0

IRA

ENA

A0–A35

CLKB

IRB

0,0

su(FS)

h(FS)

pd(C-IR)

su(D)

AFA Offset

(Y1)

su(EN)

h(D)

AEB Offset

(X1)

h(EN)

AFB Offset

(Y2)

0,1

pd(C-IR)

AEA Offset

(X2)

†

‡

sk1

First Word to FIFO1

pd(C-IR)

‡

is the minimum time between the rising CLKA edge and a rising CLKB edge for IRB to transition high in the next cycle. If the time between

sk1

the rising edge of CLKA and rising edge of CLKB is less than t

NOTE A: CSA

= L, W/RA = H, MBA = L. It is not necessary to program offset register on consecutive clock cycles.

Figure 2. Programming the Almost-Full Flag and Almost-Empty Flag Offset Values After Reset

, IRB may transition high one cycle later than shown.

sk1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

МММММММ

ООООООО

МММММММ

ППППППП

МММММММ

ООООООО

SN54ACT3632

512 × 36 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SGBS310A – SEPTEMBER 1996 – REVISED APRIL 1998

w(CLKL)

CLKA

w(CLKH)

IRA

CSA

W/RA

MBA

ENA

A0–A35

†

Written to FIFO1

CLKB

w(CLKH)

su(EN)

su(D)

w(CLKL)

h(EN)

h(D)

†

su(EN)

†

Figure 3. Port-A Write Cycle for FIFO1

su(EN)

No Operation

h(EN)

IRB

CSB

W/RB

MBB

ENB

B0–B35

‡

Written to FIFO2

su(EN)

su(D)

h(EN)

h(D)

‡

su(EN)

‡

Figure 4. Port-B Write Cycle for FIFO2

su(EN)

No Operation

h(EN)

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SN54ACT3632

ООООО

ММММММ

ООООО

512 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SGBS310A – SEPTEMBER 1996 – REVISED APRIL 1998

w(CLKL)

su(EN)

†

h(EN)

su(EN)

h(EN)

†

CLKA

ORA

CSA

W/RA

MBA

ENA

A0–A35

w(CLKH)

pd(M-DV)

su(EN)

Operation

†

h(EN)

dis

†

Read from FIFO2

CLKB

ORB

CSB

W/RB

MBB

ENB

pd(M-DV)

B0–B35

w(CLKH)

w(CLKL)

Figure 5. Port-A Read Cycle for FIFO2

su(EN)

h(EN)

‡

su(EN)

‡

h(EN)

su(EN)

Operation

‡

h(EN)

dis

‡

Read from FIFO1

Figure 6. Port-B Read Cycle for FIFO1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ACT3632

512 × 36 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SGBS310A – SEPTEMBER 1996 – REVISED APRIL 1998

CLKA

CSA

Low

w(CLKH)

w(CLKL)

W/RA

MBA

ENA

IRA

A0–A35

CLKB

ORB

CSB

W/RB

MBB

ENB

B0–B35

High

Low

High

Low

su(EN)

su(D)

†

sk1

w(CLKH)

Old Data in FIFO1 Output Register

h(EN)

h(D)

Old Data in FIFO1 Output Register

w(CLKL)

123

pd(C-OR)

su(EN)

h(EN)

pd(C-OR)

†

is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition high and to clock the next word to the FIFO1

sk1

output register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than t high and load of the first word to the output register may occur one CLKB cycle later than shown.

, the transition of ORB

sk1

Figure 7. ORB-Flag Timing and First Data-Word Fall Through When FIFO1 Is Empty

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SN54ACT3632 512 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SGBS310A – SEPTEMBER 1996 – REVISED APRIL 1998

CLKB

CSB

Low

w(CLKH)

w(CLKL)

W/RB

MBB

ENB

IRB

B0–B35

CLKA

ORA

CSA

W/RA

MBA

ENA

A0–A35

Low

High

Low

su(EN)

su(D)

†

sk1

Old Data in FIFO2 Output Register

h(EN)

h(D)

w(CLKH)

Old Data in FIFO2 Output Register

w(CLKL)

123

pd(C-OR)

su(EN)

h(EN)

pd(C-OR)

†

is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition high and to clock the next word to the FIFO2

sk1

output register in three CLKA cycles. If the time between the rising CLKB edge and rising CLKA edge is less than t high and load of the first word to the output register may occur one CLKA cycle later than shown.

, the transition of ORA

sk1

Figure 8. ORA-Flag Timing and First Data-Word Fall Through When FIFO2 Is Empty

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

w(CLKH)

CLKB

CSB

Low

SN54ACT3632

512 × 36 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SGBS310A – SEPTEMBER 1996 – REVISED APRIL 1998

w(CLKL)

W/RB

B0–B35

CLKA

W/RA

A0–A35

†

sk1

between the rising CLKB edge and rising CLKA edge is less than t

High

Low

MBB

su(EN)

ENB

ORB

High

Previous Word in FIFO1 Output Register Next Word From FIFO1

IRA

CSA

Low

High

MBA

ENA

is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition high in the next CLKA cycle. If the time

h(EN)

sk1

w(CLKH)

FIFO1 Full

†

w(CLKL)

pd(C-IR)

, IRA may transition high one CLKA cycle later than shown.

sk1

su(EN)

su(D)

To FIFO1

h(EN)

h(D)

pd(C-IR)

Figure 9. IRA-Flag Timing and First Available Write When FIFO1 Is Full

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SN54ACT3632 512 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SGBS310A – SEPTEMBER 1996 – REVISED APRIL 1998

w(CLKH)

CLKA

CSA

Low

w(CLKL)

W/RA

A0–A35

CLKB

W/RB

B0–B35

†

sk1

between the rising CLKA edge and rising CLKB edge is less than t

Low

MBA

su(EN)

ENA

High

ORA

Previous Word in FIFO2 Output Register Next Word From FIFO2

IRB

CSB

Low

MBB

ENB

is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition high in the next CLKB cycle. If the time

h(EN)

sk1

w(CLKH)

FIFO2 Full

†

w(CLKL)

pd(C-IR)

, IRB may transition high one CLKB cycle later than shown.

sk1

su(EN)

su(D)

To FIFO2

h(EN)

h(D)

pd(C-IR)

Figure 10. IRB-Flag Timing and First Available Write When FIFO2 Is Full

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CLKA

ENA

su(EN)

sk2

h(EN)

†

SN54ACT3632

512 × 36 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SGBS310A – SEPTEMBER 1996 – REVISED APRIL 1998

CLKB

AEB

ENB

†

sk2

between the rising CLKA edge and rising CLKB edge is less than t

NOTE A: FIFO1 write (CSA

X1 Words in FIFO1

is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition high in the next CLKB cycle. If the time

= L, W/RA = H, MBA = L), FIFO1 read (CSB = L, W/RB = H, MBB = L). Data in the FIFO1 output register has been

read from the FIFO.

sk2

pd(C-AE)

(X1 + 1) Words in FIFO1

, AEB

may transition high one CLKB cycle later than shown.

pd(C-AE)

su(EN)

h(EN)

Figure 11. AEB When FIFO1 Is Almost Empty

CLKB

sk2

h(EN)

‡

pd(C-AE)

(X2 + 1) Words in FIFO2

su(EN)

h(EN)

ENB

CLKA

AEA

ENA

su(EN)

X2 Words in FIFO2

‡

is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition high in the next CLKA cycle. If the time

sk2

between the rising CLKB edge and rising CLKA edge is less than t

NOTE A: FIFO2 write (CSB

read from the FIFO.

= L, W/RB = L, MBB = L), FIFO2 read (CSA = L, W/RA = L, MBA = L). Data in the FIFO2 output register has been

sk2

, AEA

may transition high one CLKA cycle later than shown.

Figure 12. AEA When FIFO2 Is Almost Empty

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ACT3632

†

‡

512 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SGBS310A – SEPTEMBER 1996 – REVISED APRIL 1998

sk2

CLKA

ENA

AFA

CLKB

ENB

su(EN)

pd(C-AF)

[512 – (Y1 + 1)] Words in FIFO1

h(EN)

(512 – Y1) Words in FIFO1

su(EN)

h(EN)

pd(C-AF)

†

is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA

sk2

between the rising CLKA edge and rising CLKB edge is less than t

NOTE A: FIFO1 write (CSA

read from the FIFO.

= L, W/RA = H, MBA = L), FIFO1 read (CSB = L, W/RB = H, MBB = L). Data in the FIFO1 output register has been

sk2

, AFA

Figure 13. AFA When FIFO1 Is Almost Full

sk2

CLKB

su(EN)

ENB

pd(C-AF)

AFB

CLKA

ENA

‡

sk2

between the rising CLKB edge and rising CLKA edge is less than t

NOTE A: FIFO2 write (CSB

[512 – (Y2 + 1)] Words in FIFO2

is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB

= L, W/RB= L, MBB = L), FIFO2 read (CSA = L, W/RA = L, MBA = L). Data in the FIFO2 output register has been

read from the FIFO.

h(EN)

(512 – Y2) Words in FIFO2

su(EN)

sk2

, AFB

may transition high one CLKB cycle later than shown.

h(EN)

may transition high one CLKA cycle later than shown.

to transition high in the next CLKA cycle. If the time

pd(C-AF)

to transition high in the next CLKB cycle. If the time

Figure 14. AFB When FIFO2 Is Almost Full

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ООООООО

ППППППП

ООООООО

A0–A35

CLKA

CSA

W/RA

MBA

ENA

CLKB

MBF1

su(EN)

su(D)

SN54ACT3632

512 × 36 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SGBS310A – SEPTEMBER 1996 – REVISED APRIL 1998

h(EN)

h(D)

pd(C-MF)

CSB

W/RB

MBB

ENB

B0–B35

su(EN)

pd(M-DV)

pd(C-MR)

h(EN)

dis

W1 (remains valid in mail1 register after read)

FIFO1 Output Register

Figure 15. Mail1 Register and MBF1 Flag

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SN54ACT3632 512 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SGBS310A – SEPTEMBER 1996 – REVISED APRIL 1998

CLKB

h(EN)

h(D)

pd(C-MF)

CSB

W/RB

MBB

ENB

B0–B35

CLKA

MBF2

su(EN)

su(D)

pd(C-MF)

CSA

W/RA

MBA

ENA

A0–A35

su(EN)

FIFO2 Output Register

pd(M-DV)

pd(C-MR)

W1 (remains valid in mail2 register after read)

h(EN)

dis

Figure 16. Mail2 Register and MBF2 Flag

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CC§

SN54ACT3632

512 × 36 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SGBS310A – SEPTEMBER 1996 – REVISED APRIL 1998

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V Input voltage range, V Output voltage range, V Input clamp current, I Output clamp current, I Continuous output current, I Continuous current through V Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

or GND ±400 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions

MIN MAX UNIT

V V V I I T

OH OL

Supply voltage 4.5 5.5 V

High-level input voltage 2 V

Low-level input voltage 0.8 V

High-level output current –4 mA Low-level output current 8 mA Operating free-air temperature –55 125 °C

†

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP‡MAX UNIT

∆I

‡

All typical values are at VCC = 5 V, TA = 25°C.

This is the supply current when each input is at one of the specified TTL voltage levels rather than 0 V or VCC.

VCC = 4.5 V, IOH = –4 mA 2.4 V VCC = 4.5 V, IOL = 8 mA 0.5 V VCC = 5.5 V, VI = VCC or 0 ±5 µA VCC = 5.5 V, VO = VCC or 0 ±5 µA VCC = 5.5 V, VI = VCC – 0.2 V or 0 400 µA

CSA = V

= 5.5 V, One input at 3.4 V , Other inputs at VCC or GND

VI = 0, f = 1 MHz 4 pF VO = 0, f = 1 MHz 8 pF

CSB = V CSA = V CSB = V All other inputs 1

IH IH IL IL

A0–A35 0 B0–B35 0 A0–A35 1 B0–B35 1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ACT3632 512 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SGBS310A – SEPTEMBER 1996 – REVISED APRIL 1998

timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Figures 1 through 17)

MIN MAX UNIT

clock

w(CLKH)

w(CLKL)

su(D)

su(EN)

su(RS)

su(FS)

h(D)

h(EN)

h(RS)

h(FS)

sk1

sk2

†

Requirement to count the clock edge as one of at least four needed to reset a FIFO

‡

Skew time is not a timing constraint for proper device operation and is included only to illustrate the timing relationship between CLKA cycle and CLKB cycle.

Clock frequency, CLKA or CLKB 50 MHz Clock cycle time, CLKA or CLKB 20 ns Pulse duration, CLKA and CLKB high 8 ns Pulse duration, CLKA and CLKB low 8 ns Setup time, A0–A35 before CLKA↑ and B0–B35 before CLKB↑ 5 ns Setup time, CSA, W/RA, ENA, and MBA before CLKA↑;

CSB

, W/RB, ENB, and MBB before CLKB↑ Setup time, RST1 or RST2 low before CLKA↑ or CLKB↑ Setup time, FS0 and FS1 before RST1 and RST2 high 8.5 ns Hold time, A0–A35 after CLKA↑ and B0–B35 after CLKB↑ 1 ns Hold time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB, W/RB, ENB, and MBB after CLKB↑ 1 ns Hold time, RST1 or RST2 low after CLKA↑ or CLKB↑ Hold time, FS0 and FS1 after RST1 and RST2 high 3 ns

‡

Skew time between CLKA↑ and CLKB↑ for ORA, ORB, IRA, and IRB 9 ns

‡

Skew time between CLKA↑ and CLKB↑ for AEA, AEB, AFA, and AFB 16 ns

†

5 ns 6 ns

4 ns

switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C

max

pd(C-IR)

pd(C-OR)

pd(C-AE)

pd(C-AF)

pd(C-MF)

pd(C-MR)

pd(M-DV)

pd(R-F)

dis

Writing data to the mail1 register when the B0–B35 outputs are active and MBB is high

Writing data to the mail2 register when the A0–A35 outputs are active and MBA is high

= 30 pF (see Figures 1 through 17)

PARAMETER

Access time, CLKA↑ to A0–A35 and CLKB↑ to B0–B35 3 15 ns Propagation delay time, CLKA↑ to IRA and CLKB↑ to IRB 2 10 ns Propagation delay time, CLKA↑ to ORA and CLKB↑ to ORB 1 10 ns Propagation delay time, CLKA↑ to AEA and CLKB↑ to AEB 1 10 ns Propagation delay time, CLKA↑ to AFA and CLKB↑ to AFB 1 10 ns Propagation delay time, CLKA↑ to MBF1 low or MBF2 high and

CLKB↑ to MBF2 Propagation delay time, CLKA↑ to B0–B35§ and CLKB↑ to A0–A35 Propagation delay time, MBA to A0–A35 valid and MBB to B0–B35 valid 3 13 ns Propagation delay time, RST1 low to AEB low, AFA high, and MBF1 high, and

RST2

low to AEA low, AFB high, and MBF2 high Enable time, CSA and W/RA low to A0–A35 active and CSB low and W/RB high to B0–B35 active 2 18 ns Disable time, CSA or W/RA high to A0–A35 at high impedance and

CSB

high or W/RB low to B0–B35 at high impedance

low or MBF1 high

MIN MAX UNIT

50 MHz

0 10 ns 3 18.7 ns

1 20 ns

1 13 ns

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ACT3632

512 × 36 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SGBS310A – SEPTEMBER 1996 – REVISED APRIL 1998

PARAMETER MEASUREMENT INFORMATION

Timing

Enable

Output

Enable

Low-Level

Output

High-Level

Output

PLZ

PHZ

1.5 V

Input

Data,

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

1.5 V 1.5 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Load

Output Under Test

(see Note A)

LOAD CIRCUIT

3 V

GND

3 V

1.5 V1.5 V GND

3 V

GND

PZL

≈ 3 V

1.5 V V

PZH

1.5 V ≈ 0 V

High-Level

Input

Low-Level

Input

In-Phase

Output

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PULSE DURATIONS

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

3 V

GND

3 V

GND

3 V

GND

1.5 V1.5 V V

NOTES: A. Includes probe and jig capacitance

B. t C. t

PZL PLZ

and t and t

are the same as ten.

PZH

are the same as t

PHZ

PARAMETER

†

Includes probe and test-fixture capacitance

Figure 17. Load Circuit and Voltage Waveforms

dis

CONDITIONS FOR LOAD CIRCUIT

(mA)

Load

(V)

(mA)

PZH

PZL

PHZ

PLZ

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8 4 0 20 4 8 3 20 8 6 1.5 20 8 6 1.5 20 4 8 1.5 20

†

(typical)

(pF)

SN54ACT3632 512 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SGBS310A – SEPTEMBER 1996 – REVISED APRIL 1998

TYPICAL CHARACTERISTICS

SUPPLY CURRENT

CLOCK FREQUENCY

300

= 1/2 f

data

TA = 75°C CL = 0 pF

250

200

150

– Supply Current – mA

100

CC(f)

clock

VCC = 5.5 V

VCC = 5 V

VCC = 4.5 V

0 10203040506070

– Clock Frequency – MHz

clock

Figure 18

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IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MA Y INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO BE FULLY AT THE CUSTOMER’S RISK.

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Datasheet SN54ACT3632HFP Datasheet (Texas Instruments)

Specifications and Main Features

Frequently Asked Questions

User Manual