SN54ABT541, SN74ABT541B
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS093K – JANUARY 1991 – REVISED OCTOBER 1998
D
State-of-the-Art
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D
T ypical V
at V
D
High-Impedance State During Power Up
= 5 V, TA = 25°C
CC
(Output Ground Bounce) < 1 V
OLP
and Power Down
D
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Ceramic Flat (W) Package, and Plastic (N)
and Ceramic (J) DIPs
description
The SN54ABT541 and SN74ABT541B octal
buffers and line drivers are ideal for driving bus
lines or buffering memory address registers. The
devices feature inputs and outputs on opposite
sides of the package to facilitate printed circuit
board layout.
The 3-state control gate is a two-input AND gate
with active-low inputs so that if either
output-enable (OE1
outputs are in the high-impedance state.
or OE2) input is high, all eight
SN54ABT541 ...J OR W PACKAGE
SN74ABT541B . . . DB, DW, N, OR PW PACKAGE
SN54ABT541 . . . FK PACKAGE
A3
A4
A5
A6
A7
(TOP VIEW)
OE1
A1
A2
A3
A4
A5
A6
A7
A8
GND
(TOP VIEW)
3 2 1 20 19
4
5
6
7
8
910111213
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
A2A1OE1
A8
V
Y8
GND
CC
Y7
V
CC
OE2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
18
17
16
15
14
Y6 OE2
Y1
Y2
Y3
Y4
Y5
When V
However, to ensure the high-impedance state above 2.1 V, OE
is between 0 and 2.1 V , the device is in the high-impedance state during power up or power down.
CC
should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT541 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT541B is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
OE1 OE2 A
L L L L
L LH H
HXX Z
XHX Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
INPUTS
OUTPUT
Y
Copyright 1998, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54ABT541, SN74ABT541B
UNIT
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS093K – JANUARY 1991 – REVISED OCTOBER 1998
1
19
2
3
4
5
6
7
8
9
†
&
EN
1
18
17
16
15
14
13
12
11
logic symbol
OE1
OE2
A1
A2
A3
A4
A5
A6
A7
A8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
logic diagram (positive logic)
OE1
OE2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
1
19
218
A1
Y1
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Voltage range applied to any output in the high or power-off state, V
Current into any output in the low state, I
Input clamp current, I
Output clamp current, I
Package thermal impedance, θ
Storage temperature range, T
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
: SN54ABT541 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
–0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
O
SN74ABT541B 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
(see Note 2): DB package 115°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 128°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
‡
recommended operating conditions (see Note 3)
SN54ABT541 SN74ABT541B
MIN MAX MIN MAX
V
V
V
I
OH
I
OL
T
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
2
Supply voltage 4.5 5.5 4.5 5.5 V
CC
High-level input voltage 2 2 V
IH
Low-level input voltage 0.8 0.8 V
IL
High-level output current –24 –32 mA
Low-level output current 48 64 mA
Operating free-air temperature –55 125 –40 85 ° C
A
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER
TEST CONDITIONS
UNIT
V
V
V
4.5 V
V
V
V
V
V
I
V
CC
GND
§
V
CC
CC
A
Y
ns
OE
Y
ns
OE
Y
ns
SN54ABT541, SN74ABT541B
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS093K – JANUARY 1991 – REVISED OCTOBER 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54ABT541 SN74ABT541B
MIN TYP†MAX MIN MAX MIN MAX
V
IK
OH
OL
V
hys
I
I
I
OZPU
I
OZPD
I
OZH
I
OZL
I
off
I
CEX
‡
I
O
I
CC
∆I
CC
C
i
C
o
* On products compliant to MIL-PRF-38535, this parameter does not apply.
** On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
All typical values are at VCC = 5 V.
‡
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
§
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5
VCC = 5 V, IOH = –3 mA 3 3 3
=
CC
= 4.5
CC
VCC = 5.5 V, VI = VCC or GND ±1 ±1 ±1 µA
VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X ±50** ±50** ±50 µA
VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X ±50** ±50** ±50 µA
VCC = 5.5 V, VO = 2.7 V 10 10 10 µA
VCC = 5.5 V, VO = 0.5 V –10 –10 –10 µA
VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA
VCC = 5.5 V, VO = 5.5 V Outputs high 50 50 50 µA
VCC = 5.5 V, VO = 2.5 V –50 –140 –180 –50 –180 –50 –180 mA
VCC = 5.5 V, IO = 0,
=
or
=
= 5.5 V,
One input at 3.4 V ,
Other inputs at VCC or GND
VI = 2.5 V or 0.5 V 3 pF
VO = 2.5 V or 0.5 V 6 pF
IOH = –24 mA 2 2
IOH = –32 mA 2* 2
IOL = 48 mA 0.55 0.55
IOL = 64 mA 0.55* 0.55
100 mV
Outputs high 5 250 250 250 µA
Outputs low 22 30 30 30 mA
Outputs disabled 1 250 250 250 µA
Outputs enabled 1.5 1.5 1.5 mA
Outputs disabled 50 50 50 µA
Control inputs 1.5 1.5 1.5 mA
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
PARAMETER
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
= 50 pF (unless otherwise noted) (see Figure 1)
L
FROM
(INPUT)
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TO
(OUTPUT)
SN54ABT541
VCC = 5 V,
TA = 25°C
MIN TYP MAX
1 2.6 4.1 1 4.6
1 2.9 4.2 1 4.7
1.1 3.1 4.8 1.1 5.4
2.1 4.4 5.9 2.1 7
2.1 5.1 6.6 2.1 7.5
1.7 4.7 6.2 1.7 6.7
MIN MAX
UNIT
3
SN54ABT541, SN74ABT541B
A
Y
ns
OE
Y
ns
OE
Y
ns
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS093K – JANUARY 1991 – REVISED OCTOBER 1998
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
PARAMETER
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
sk(o)
†
Skew between any two outputs of the same package switching in the same direction
= 50 pF (unless otherwise noted) (see Figure 1)
L
FROM
(INPUT)
†
TO
(OUTPUT)
SN74ABT541B
VCC = 5 V,
TA = 25°C
MIN TYP MAX
1 2 3.2 1 3.6
1 2.6 3.5 1 3.9
2 3.5 4.5 2 4
1.9 4 5.1 1.9 5.9
2.2 4.4 5.4 2.2 5.8
1.5 3 4 1.5 4.4
MIN MAX
0.5 0.5 ns
UNIT
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT541, SN74ABT541B
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS093K – JANUARY 1991 – REVISED OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION
500 Ω
t
w
1.5 V
500 Ω
1.5 V
1.5 V
1.5 V1.5 V
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Input
Input
Output
Output
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V 1.5 V
t
PLH
t
PHL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
S1
t
PHL
t
PLH
3 V
0 V
V
V
V
V
7 V
OH
OL
OH
OL
Open
GND
3 V
0 V
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
PZL
t
PLZ
1.5 V
t
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
PHZ
1.5 V
Open
Open
1.5 V
t
7 V
h
1.5 V1.5 V
VOL + 0.3 V
VOH – 0.3 V
3 V
0 V
3 V
0 V
3 V
0 V
3.5 V
V
OL
V
OH
≈ 0 V
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jun-2005
PACKAGING INFORMATION
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
5962-9471801Q2A ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NC
5962-9471801QRA ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NC
5962-9471801QSA ACTIVE CFP W 20 1 TBD Call TI Level-NC-NC-NC
SN74ABT541BDBLE OBSOLETE SSOP DB 20 TBD Call TI Call TI
SN74ABT541BDBR ACTIVE SSOP DB 20 2000 Pb-Free
SN74ABT541BDBRE4 ACTIVE SSOP DB 20 2000 Pb-Free
SN74ABT541BDBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS &
no Sb/Br)
SN74ABT541BDW ACTIVE SOIC DW 20 25 Pb-Free
SN74ABT541BDWE4 ACTIVE SOIC DW 20 25 Pb-Free
SN74ABT541BDWR ACTIVE SOIC DW 20 2000 Pb-Free
SN74ABT541BDWRE4 ACTIVE SOIC DW 20 2000 Pb-Free
SN74ABT541BN ACTIVE PDIP N 20 20 Pb-Free
SN74ABT541BNSR ACTIVE SO NS 20 2000 Pb-Free
SN74ABT541BNSRE4 ACTIVE SO NS 20 2000 Pb-Free
SN74ABT541BPW ACTIVE TSSOP PW 20 70 Pb-Free
SN74ABT541BPWE4 ACTIVE TSSOP PW 20 70 Pb-Free
SN74ABT541BPWLE OBSOLETE TSSOP PW 20 TBD Call TI Call TI
SN74ABT541BPWR ACTIVE TSSOP PW 20 2000 Pb-Free
SN74ABT541BPWRE4 ACTIVE TSSOP PW 20 2000 Pb-Free
SNJ54ABT541FK ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NC
SNJ54ABT541J ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NC
SNJ54ABT541W ACTIVE CFP W 20 1 TBD Call TI Level-NC-NC-NC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(RoHS)
(RoHS)
(RoHS)
(RoHS)
(RoHS)
(RoHS)
(RoHS)
(RoHS)
(RoHS)
(RoHS)
(RoHS)
(RoHS)
(RoHS)
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
CU NIPDAU Level-2-260C-1YEAR
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
CU NIPDAU Level-NC-NC-NC
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
CU NIPDAU Level-1-250C-UNLIM
CU NIPDAU Level-1-250C-UNLIM
CU NIPDAU Level-1-250C-UNLIM
CU NIPDAU Level-1-250C-UNLIM
(3)
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
8-Jun-2005
Addendum-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A SQ
B SQ
19
20
21
22
23
24
25
12826 27
12
1314151618 17
0.020 (0,51)
0.010 (0,25)
MIN
0.342
(8,69)
0.442
0.640
0.739
0.938
1.141
A
0.358
(9,09)
0.458
(11,63)
0.660
(16,76)
0.761
(19,32)(18,78)
0.962
(24,43)
1.165
(29,59)
(10,31)
(12,58)
(12,58)
NO. OF
TERMINALS
**
11
10
9
8
7
6
5
432
20
28
44
52
68
84
0.020 (0,51)
0.010 (0,25)
(11,23)
(16,26)
(23,83)
(28,99)
MINMAX
0.307
(7,80)
0.406
0.495
0.495
0.850
(21,6)
1.047
(26,6)
0.080 (2,03)
0.064 (1,63)
B
MAX
0.358
(9,09)
0.458
(11,63)
0.560
(14,22)
0.560
(14,22)
0.858
(21,8)
1.063
(27,0)
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
4040140/D 10/96
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,65
28
1
2,00 MAX
0,38
0,22
15
14
A
0,05 MIN
0,15
5,60
5,00
M
8,20
7,40
Seating Plane
0,10
0,25
0,09
0°–ā8°
Gage Plane
0,25
0,95
0,55
PINS **
DIM
A MAX
A MIN
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
14
6,50
6,50
5,905,90
2016
7,50
6,90
24
8,50
28
10,50
9,907,90
30
10,50
9,90
38
12,90
12,30
4040065 /E 12/01
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65
1,20 MAX
14
0,30
0,19
8
4,50
4,30
PINS **
7
Seating Plane
0,15
0,05
8
1
A
DIM
6,60
6,20
14
0,10
M
0,10
0,15 NOM
0°–8°
2016
Gage Plane
24
0,25
0,75
0,50
28
A MAX
A MIN
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
4040064/F 01/97
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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