TEXAS INSTRUMENTS SN54ABT541, SN74ABT541B Technical data

SN54ABT541, SN74ABT541B

OCTAL BUFFERS/DRIVERS

WITH 3-STATE OUTPUTS

SCBS093K – JANUARY 1991 – REVISED OCTOBER 1998

D

State-of-the-Art

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

D

Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17

D

T ypical V
at V

D

High-Impedance State During Power Up

= 5 V, TA = 25°C

CC

(Output Ground Bounce) < 1 V

OLP

and Power Down

D

High-Drive Outputs (–32-mA IOH, 64-mA IOL)

D

Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Ceramic Flat (W) Package, and Plastic (N)
and Ceramic (J) DIPs

description

The SN54ABT541 and SN74ABT541B octal
buffers and line drivers are ideal for driving bus
lines or buffering memory address registers. The
devices feature inputs and outputs on opposite
sides of the package to facilitate printed circuit
board layout.

The 3-state control gate is a two-input AND gate
with active-low inputs so that if either
output-enable (OE1
outputs are in the high-impedance state.

or OE2) input is high, all eight

SN54ABT541 ...J OR W PACKAGE

SN74ABT541B . . . DB, DW, N, OR PW PACKAGE

SN54ABT541 . . . FK PACKAGE

A3
A4
A5
A6
A7

(TOP VIEW)

OE1

A1
A2
A3
A4
A5
A6
A7
A8

GND

(TOP VIEW)

3 2 1 20 19

4
5
6
7
8

910111213

1

20

2

19

3

18

4

17

5

16

6

15

7

14

8

13

9

12

10

11

A2A1OE1

A8

V

Y8

GND

CC

Y7

V

CC

OE2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8

18
17
16
15
14

Y6 OE2

Y1
Y2
Y3
Y4
Y5

When V
However, to ensure the high-impedance state above 2.1 V, OE

is between 0 and 2.1 V , the device is in the high-impedance state during power up or power down.

CC

should be tied to VCC through a pullup resistor;

the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT541 is characterized for operation over the full military temperature range of –55°C to 125°C.

The SN74ABT541B is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

OE1 OE2 A

L L L L

L LH H
HXX Z
XHX Z

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

INPUTS

OUTPUT

Y

Copyright  1998, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

SN54ABT541, SN74ABT541B

UNIT

OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS

SCBS093K – JANUARY 1991 – REVISED OCTOBER 1998

1

19

2
3
4
5
6
7
8
9

†

&

EN

1

18
17
16
15
14
13
12
11

logic symbol

OE1

OE2

A1
A2
A3
A4
A5
A6
A7
A8

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.

logic diagram (positive logic)

OE1
OE2

Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8

1
19

218

A1

Y1

To Seven Other Channels

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Input voltage range, V
Voltage range applied to any output in the high or power-off state, V
Current into any output in the low state, I

Input clamp current, I
Output clamp current, I
Package thermal impedance, θ

Storage temperature range, T

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

: SN54ABT541 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

–0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .

O

SN74ABT541B 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OK

(see Note 2): DB package 115°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 128°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

‡

recommended operating conditions (see Note 3)

SN54ABT541 SN74ABT541B

MIN MAX MIN MAX

V
V
V
I

OH

I

OL

T

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

2

Supply voltage 4.5 5.5 4.5 5.5 V

CC

High-level input voltage 2 2 V

IH

Low-level input voltage 0.8 0.8 V

IL

High-level output current –24 –32 mA
Low-level output current 48 64 mA
Operating free-air temperature –55 125 –40 85 ° C

A

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER

TEST CONDITIONS

UNIT

V

V

V

4.5 V

V

V

V

V

V

I

V

CC

GND

§

V

CC

CC

A

Y

ns

OE

Y

ns

OE

Y

ns

SN54ABT541, SN74ABT541B

OCTAL BUFFERS/DRIVERS

WITH 3-STATE OUTPUTS

SCBS093K – JANUARY 1991 – REVISED OCTOBER 1998

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

TA = 25°C SN54ABT541 SN74ABT541B

MIN TYP†MAX MIN MAX MIN MAX

V

IK

OH

OL

V

hys

I

I

I

OZPU

I

OZPD

I

OZH

I

OZL

I

off

I

CEX

‡

I

O

I

CC

∆I

CC

C

i

C

o

* On products compliant to MIL-PRF-38535, this parameter does not apply.
** On products compliant to MIL-PRF-38535, this parameter is not production tested.

†

All typical values are at VCC = 5 V.

‡

Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

§

This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5
VCC = 5 V, IOH = –3 mA 3 3 3

=

CC

= 4.5

CC

VCC = 5.5 V, VI = VCC or GND ±1 ±1 ±1 µA
VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X ±50** ±50** ±50 µA
VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X ±50** ±50** ±50 µA
VCC = 5.5 V, VO = 2.7 V 10 10 10 µA
VCC = 5.5 V, VO = 0.5 V –10 –10 –10 µA
VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA
VCC = 5.5 V, VO = 5.5 V Outputs high 50 50 50 µA
VCC = 5.5 V, VO = 2.5 V –50 –140 –180 –50 –180 –50 –180 mA

VCC = 5.5 V, IO = 0,

=

or

=

= 5.5 V,
One input at 3.4 V ,
Other inputs at VCC or GND

VI = 2.5 V or 0.5 V 3 pF
VO = 2.5 V or 0.5 V 6 pF

IOH = –24 mA 2 2
IOH = –32 mA 2* 2
IOL = 48 mA 0.55 0.55
IOL = 64 mA 0.55* 0.55

100 mV

Outputs high 5 250 250 250 µA
Outputs low 22 30 30 30 mA
Outputs disabled 1 250 250 250 µA
Outputs enabled 1.5 1.5 1.5 mA
Outputs disabled 50 50 50 µA
Control inputs 1.5 1.5 1.5 mA

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C

PARAMETER

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

= 50 pF (unless otherwise noted) (see Figure 1)

L

FROM

(INPUT)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TO

(OUTPUT)

SN54ABT541

VCC = 5 V,

TA = 25°C

MIN TYP MAX

1 2.6 4.1 1 4.6
1 2.9 4.2 1 4.7

1.1 3.1 4.8 1.1 5.4

2.1 4.4 5.9 2.1 7

2.1 5.1 6.6 2.1 7.5

1.7 4.7 6.2 1.7 6.7

MIN MAX

UNIT

3

SN54ABT541, SN74ABT541B

A

Y

ns

OE

Y

ns

OE

Y

ns

OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS

SCBS093K – JANUARY 1991 – REVISED OCTOBER 1998

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C

PARAMETER

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

t

sk(o)

†

Skew between any two outputs of the same package switching in the same direction

= 50 pF (unless otherwise noted) (see Figure 1)

L

FROM

(INPUT)

†

TO

(OUTPUT)

SN74ABT541B

VCC = 5 V,

TA = 25°C

MIN TYP MAX

1 2 3.2 1 3.6
1 2.6 3.5 1 3.9
2 3.5 4.5 2 4

1.9 4 5.1 1.9 5.9

2.2 4.4 5.4 2.2 5.8

1.5 3 4 1.5 4.4

MIN MAX

0.5 0.5 ns

UNIT

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABT541, SN74ABT541B

OCTAL BUFFERS/DRIVERS

WITH 3-STATE OUTPUTS

SCBS093K – JANUARY 1991 – REVISED OCTOBER 1998

PARAMETER MEASUREMENT INFORMATION

500 Ω

t

w

1.5 V

500 Ω

1.5 V

1.5 V

1.5 V1.5 V

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

Input

Input

Output

Output

INVERTING AND NONINVERTING OUTPUTS

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.

1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

1.5 V 1.5 V

t

PLH

t

PHL

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

S1

t

PHL

t

PLH

3 V

0 V

V

V

V

V

7 V

OH

OL

OH

OL

Open

GND

3 V

0 V

Timing Input

Data Input

Output

Control

Output

Waveform 1

S1 at 7 V

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

TEST S1

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

t

su

1.5 V 1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

t

PZL

t

PLZ

1.5 V

t

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

PHZ

1.5 V

Open

Open

1.5 V

t

7 V

h

1.5 V1.5 V

VOL + 0.3 V

VOH – 0.3 V

3 V

0 V

3 V

0 V

3 V

0 V

3.5 V

V

OL

V

OH

≈ 0 V

Figure 1. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5