TEXAS INSTRUMENTS SN54ABT16543 Technical data

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SN54ABT16543, SN74ABT16543

16-BIT REGISTERED TRANSCEIVERS

WITH 3-STATE OUTPUTS

SCBS087C – FEBRUARY 1991 – REVISED JANUARY 1997

Members of the Texas Instruments

Widebus

State-of-the-Art

 Family

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17

T ypical V

(Output Ground Bounce) < 1 V

OLP

at VCC = 5 V, TA = 25°C

Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise

Flow-Through Architecture Optimizes PCB Layout

High-Drive Outputs (–32-mA IOH, 64-mA IOL)

Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings

description

The ’ABT16543 16-bit registered transceivers contain two sets of D-type latches for temporary storage of data flowing in either direction. The ’ABT16543 can be used as two 8-bit transceivers or one 16-bit transceiver. Separate latch-enable (LEAB

or LEBA) and output-enable (OEAB or

OEBA

) inputs are provided for each register to permit independent control in either direction of data flow.

The A-to-B enable (CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches in the storage mode. With CEAB B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar but requires using the CEBA, LEBA, and OEBA inputs.

and OEAB both low, the 3-state

SN54ABT16543 . . . WD PACKAGE

SN74ABT16543 . . . DGG OR DL PACKAGE

1OEAB

1LEAB

1CEAB

2CEAB

2LEAB

2OEAB

GND

1A1 1A2

1A3 1A4 1A5

GND

1A6 1A7 1A8 2A1 2A2 2A3

GND

2A4 2A5 2A6

2A7 2A8

GND

(TOP VIEW)

1OEBA 1LEBA 1CEBA GND 1B1 1B2 V

1B3 1B4 1B5 GND 1B6 1B7 1B8 2B1 2B2 2B3 GND 2B4 2B5 2B6 V

2B7 2B8 GND 2CEBA 2LEBA 2OEBA

T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT16543 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ABT16543 is characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABT16543, SN74ABT16543 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

SCBS087C – FEBRUARY 1991 – REVISED JANUARY 1997

FUNCTION TABLE

(each 8-bit section)

INPUTS

CEAB LEAB OEAB A

H X X X Z X XHX Z

L HLXB L LLL L L L L H H

†

A-to-B data flow is shown; B-to-A flow control is the same except that it uses CEBA

‡

Output level before the indicated steady-state input conditions were established

†

OUTPUT

‡

, LEBA, and OEBA.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABT16543, SN74ABT16543

16-BIT REGISTERED TRANSCEIVERS

WITH 3-STATE OUTPUTS

SCBS087C – FEBRUARY 1991 – REVISED JANUARY 1997

logic symbol

†

1OEBA 1CEBA

1LEBA 1OEAB 1CEAB

1LEAB 2OEBA 2CEBA

2LEBA 2OEAB 2CEAB

2LEAB

1A1

1A2 1A3 1A4 1A5 1A6 1A7 1A8

2A1

2A2 2A3 2A4 2A5 2A6 2A7 2A8

56 54 55 1 3 2 29 31 30 28 26 27

6 8 9 10 12 13 14

16 17 19 20 21 23 24

1EN3 G1 1C5 2EN4 G2 2C6 7EN9 G7 7C11 8EN10 G8 8C12

12D

5D 4

11D 10

51 49 48 47 45 44 43

41 40 38 37 36 34 33

1B1

1B2 1B3 1B4 1B5 1B6 1B7 1B8

2B1

2B2 2B3 2B4 2B5 2B6 2B7 2B8

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABT16543, SN74ABT16543 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

SCBS087C – FEBRUARY 1991 – REVISED JANUARY 1997

logic diagram (positive logic)

1OEBA

1CEBA

1LEBA

1OEAB

1CEAB

1LEAB

1A1

2OEBA

55 1

C1 1D

To Seven Other Channels

C1 1D

1B1

2CEBA

2LEBA

2OEAB

2CEAB

2LEAB

2A1

30 28

C1 1D

To Seven Other Channels

C1 1D

2B1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UNIT

SN54ABT16543, SN74ABT16543

16-BIT REGISTERED TRANSCEIVERS

WITH 3-STATE OUTPUTS

SCBS087C – FEBRUARY 1991 – REVISED JANUARY 1997

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

Input voltage range, VI (except I/O ports) (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .

Current into any output in the low state, IO: SN54ABT16543 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN74ABT16543 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 2): DGG package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions (see Note 3)

SN54ABT16543 SN74ABT16543

MIN MAX MIN MAX

V V V V I

∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V T

NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.

Supply voltage 4.5 5.5 4.5 5.5 V

High-level input voltage 2 2 V

Low-level input voltage 0.8 0.8 V

Input voltage 0 V

High-level output current –24 –32 mA Low-level output current 48 64 mA

Operating free-air temperature –55 125 –40 85 °C

0 V

†

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABT16543, SN74ABT16543

PARAMETER

TEST CONDITIONS

UNIT

4.5 V

VOLV

CC,ICC

LEAB↑

LEBA↑

Hold ti

LEAB↑

LEBA↑

16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

SCBS087C – FEBRUARY 1991 – REVISED JANUARY 1997

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

TA = 25°C SN54ABT16543 SN74ABT16543

MIN TYP†MAX MIN MAX MIN MAX

hys

Control

OZH

OZL

off

CEX

∆I

C C

* On products compliant to MIL-PRF-38535, this parameter does not apply. ** These limits apply only to the SN74ABT16543.

†

All typical values are at VCC = 5 V.

‡

The parameters I

Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

inputs A or B ports

‡

A or B ports

Control

inputs A or B ports VO = 2.5 V or 0.5 V 8.5 pF

VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5 VCC = 5 V, IOH = –3 mA 3 3 3

= 4.5

= 5.5 V, V

VCC = 5.5 V, VO = 2.7 V 50** 10 50 µA VCC = 5.5 V, VO = 0.5 V –50** –10 –50 µA VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA VCC = 5.5 V,

VO = 5.5 V VCC = 5.5 V, VO = 2.5 V –50 –100 –200 –50 –200 –50 –200 mA

= 5.5 V, IO = 0, VI = VCC or GND

VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND

VI = 2.5 V or 0.5 V 3 pF

OZH

and I

include the input leakage current.

OZL

IOH = –24 mA 2 2 IOH = –32 mA 2* 2 IOL = 48 mA 0.55 0.55 IOL = 64 mA 0.55* 0.55

100 mV

= V

or GND

Outputs high 50 50 50 µA

Outputs high 2 2 2 Outputs low 35 35 35 Outputs disabled 2 2 2

±1 ±1 ±1

±100 ±100 ±100

0.5 0.5 0.5 mA

timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1)

Pulse duration, LEAB or LEBA low 4 4 4 ns

etup time, data before

me, data after

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

High 1.5 1.5 1.5 Low 3.5 3.5 3.5 High 1.5 1.5 1.5 Low 2 2 2

VCC = 5 V,

TA = 25°C MIN MAX MIN MAX MIN MAX

SN54ABT16543 SN74ABT16543

UNIT

A or B

B or A

A or B

B or A

A or B

SN54ABT16543, SN74ABT16543

16-BIT REGISTERED TRANSCEIVERS

WITH 3-STATE OUTPUTS

SCBS087C – FEBRUARY 1991 – REVISED JANUARY 1997

switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C

PARAMETER

PLH

PHL

PLH

PHL

PZH

PZL

PHZ

PLZ

PZH

PZL

PHZ

PLZ

= 50 pF (unless otherwise noted) (see Figure 1)

FROM

(INPUT)

(OUTPUT)

SN54ABT16543

VCC = 5 V,

TA = 25°C

MIN TYP MAX

0.8 2.5 3.3 0.8 3.9

0.9 2.7 4.4 0.9 5.2 1 3.1 4.3 1 5.3

1.2 3.3 4.8 1.2 5.7

0.8 3.4 4.3 0.8 5.3

1.1 3.8 7 1.1 7.9

1.9 4 6.3 1.9 7.2

1.6 3.3 4.6 1.6 5

0.9 3.8 4.9 0.9 6.3

1.2 4.2 6.8 1.2 7.9 2 4.5 6.4 2 7.3

1.7 3.9 5.1 1.7 5.6

MIN MAX

UNIT

switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C

PARAMETER

PLH

PHL

PLH

PHL

PZH

PZL

PHZ

PLZ

PZH

PZL

PHZ

PLZ

= 50 pF (unless otherwise noted) (see Figure 1)

FROM

(INPUT)

(OUTPUT)

SN74ABT16543

VCC = 5 V,

TA = 25°C

MIN TYP MAX

1 2.5 3.3 1 3.8 1 2.7 4.4 1 5.1 1 3.1 4.3 1 5.2

1.2 3.3 4.8 1.2 5.6 1 3.4 4.3 1 5.2

1.1 3.8 5.9 1.1 7

1.9 4 5 1.9 5.7

1.6 3.3 4.2 1.6 4.6 1 3.8 4.9 1 6.2

1.2 4.2 6.5 1.2 7.8 2 4.5 5.6 2 6.6

1.7 3.9 5.1 1.7 5.4

MIN MAX

UNIT

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABT16543, SN74ABT16543 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

SCBS087C – FEBRUARY 1991 – REVISED JANUARY 1997

PARAMETER MEASUREMENT INFORMATION

500 Ω

1.5 V

500 Ω

1.5 V

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

Input

Output

INVERTING AND NONINVERTING OUTPUTS

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement.

1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

1.5 V 1.5 V

PLH

PHL

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

PHL

1.5 V

PLH

1.5 V1.5 V

3 V

0 V

7 V

Open

GND

3 V

0 V

Timing Input

Data Input

Output

Control

Output

Waveform 1

S1 at 7 V

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

TEST S1

PLH/tPHL

PLZ/tPZL

PHZ/tPZH

1.5 V 1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

PZL

PLZ

1.5 V

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

PHZ

1.5 V

Open

1.5 V

7 V

1.5 V1.5 V

VOL + 0.3 V

VOH – 0.3 V

3 V

0 V

3 V

0 V

3 V

0 V

3.5 V

≈ 0 V

Figure 1. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

26-Sep-2005

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package Drawing

Pins Package

Qty

Eco Plan

5962-9324101MXA ACTIVE CFP WD 56 1 TBD Call TI Level-NC-NC-NC

74ABT16543DGGRE4 ACTIVE TSSOP DGG 56 2000 Green (RoHS &

no Sb/Br)

SN74ABT16543DGGR ACTIVE TSSOP DGG 56 2000 Green(RoHS &

no Sb/Br)

SN74ABT16543DL ACTIVE SSOP DL 56 20 Green (RoHS &

no Sb/Br)

SN74ABT16543DLG4 ACTIVE SSOP DL 56 20 Green (RoHS &

no Sb/Br)

SN74ABT16543DLR ACTIVE SSOP DL 56 1000 Green (RoHS &

no Sb/Br)

SN74ABT16543DLRG4 ACTIVE SSOP DL 56 1000 Green (RoHS &

no Sb/Br)

SNJ54ABT16543WD ACTIVE CFP WD 56 1 TBD Call TI Level-NC-NC-NC

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-1-260C-UNLIM

(3)

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

MECHANICAL DATA

MCFP010B – JANUARY 1995 – REVISED NOVEMBER 1997

WD (R-GDFP-F**) CERAMIC DUAL FLATPACK

48 LEADS SHOWN

0.120 (3,05)

0.075 (1,91)

0.370 (9,40)

0.250 (6,35)

0.009 (0,23)

0.004 (0,10)

1.130 (28,70)

0.870 (22,10)

0.390 (9,91)

0.370 (9,40)

0.250 (6,35)

0.025 (0,635)

0.014 (0,36)

0.008 (0,20)

NO. OF

LEADS**

A MAX

A MIN

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification only

E. Falls within MIL STD 1835: GDFP1-F48 and JEDEC MO-146AA

GDFP1-F56 and JEDEC MO-146AB

(16,26)

0.610

(15,49)

0.7400.640

(18,80)

0.710

(18,03)

4040176/D 10/97

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001

DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

48 PINS SHOWN

0.025 (0,635)

0.110 (2,79) MAX

0.0135 (0,343)

0.008 (0,203) 25

0.299 (7,59)

0.291 (7,39)

0.008 (0,20) MIN

0.005 (0,13)

0.420 (10,67)

0.395 (10,03)

Seating Plane

0.004 (0,10)

0.010 (0,25)

0.005 (0,13)

Gage Plane

0.010 (0,25)

0°–ā8°

0.040 (1,02)

0.020 (0,51)

PINS **

DIM

A MAX

A MIN

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). D. Falls within JEDEC MO-118

0.380 (9,65)

0.370 (9,40)

4828

0.630

(16,00)

0.620

(15,75)

0.730

(18,54)

0.720

(18,29)

4040048/E 12/01

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MTSS003D – JANUARY 1995 – REVISED JANUARY 1998

DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

48 PINS SHOWN

0,50

1,20 MAX

0,27 0,17

0,15 0,05

0,08

6,20

8,30

6,00

7,90

Seating Plane

0,10

0,15 NOM

Gage Plane

0,25

0°–8°

0,75 0,50

DIM

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Body dimensions do not include mold protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

PINS **

A MAX

A MIN

12,60

12,40

14,10

13,90

17,10

16,90

4040078/F 12/97

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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TEXAS INSTRUMENTS SN54ABT16543 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual